公开(公告)号：US20190042452A1

公开(公告)日：2019-02-07

申请号：US16143734

申请日：2018-09-27

Applicant: Intel Corporation

Inventor： Chace Clark ,  Francis Corrado

IPC: G06F12/0888 ,  G06F12/0804 ,  G06F12/0866 ,  G06F13/16 ,  G06F3/06

Abstract: An embodiment of a semiconductor apparatus may include technology to determine workload-related information for a persistent storage media and a cache memory, and aggregate a bandwidth of the persistent storage media and the cache memory based on the determined workload information. Other embodiments are disclosed and claimed.

公开(公告)号：US20220004495A1

公开(公告)日：2022-01-06

申请号：US17475984

申请日：2021-09-15

Applicant: Intel Corporation

Inventor： Shankar Natarajan ,  Chace Clark ,  Francis Corrado ,  Shivashekar Muralishankar ,  Suresh Nagarajan

IPC: G06F12/0802 ,  G06F3/06

Abstract: Systems, apparatuses, and methods provide for a memory controller to manage cache evictions and/or insertions in a data server environment based at least in part on host managed hotness data. For example, a memory controller includes logic to receive a plurality of read and write requests from a host, where the plurality of read and write requests include an associated hotness data. A valid unit count of operational memory cells is maintained on a block-by-block basis for a plurality of memory blocks. A hotness index count is also maintained based at least in part on the hotness data on a block-by-block basis for the plurality of memory blocks. One or more memory blocks of the plurality of memory blocks are selected for eviction from a single level cell region to an x-level cell region based at least in part on the valid unit count and the hotness index count.

公开(公告)号：US20210232313A1

公开(公告)日：2021-07-29

申请号：US17231893

申请日：2021-04-15

Applicant: Intel Corporation

Inventor： Chace A. Clark ,  Francis Corrado

IPC: G06F3/06

Abstract: An embodiment of an electronic apparatus may include one or more substrates; and a controller coupled to the one or more substrates, the controller including logic to control access to a NAND-based storage media that includes a first cell region with a first number of levels and a second region with a second number of levels that is different from the first number of levels, determine logical block address locations that correspond to a user configurable capacity placeholder, and adjust respective sizes of the first cell region and the second cell region at runtime based on the logical block address locations. Other embodiments are disclosed and claimed.

公开(公告)号：US11003582B2

公开(公告)日：2021-05-11

申请号：US16143734

申请日：2018-09-27

Applicant: Intel Corporation

Inventor： Chace Clark ,  Francis Corrado

IPC: G06F12/0888 ,  G06F12/0804 ,  G06F12/0866 ,  G06F13/16 ,  G06F3/06

Abstract: An embodiment of a semiconductor apparatus may include technology to determine workload-related information for a persistent storage media and a cache memory, and aggregate a bandwidth of the persistent storage media and the cache memory based on the determined workload information. Other embodiments are disclosed and claimed.