公开(公告)号：US20220004495A1

公开(公告)日：2022-01-06

申请号：US17475984

申请日：2021-09-15

Applicant: Intel Corporation

Inventor： Shankar Natarajan ,  Chace Clark ,  Francis Corrado ,  Shivashekar Muralishankar ,  Suresh Nagarajan

IPC: G06F12/0802 ,  G06F3/06

Abstract: Systems, apparatuses, and methods provide for a memory controller to manage cache evictions and/or insertions in a data server environment based at least in part on host managed hotness data. For example, a memory controller includes logic to receive a plurality of read and write requests from a host, where the plurality of read and write requests include an associated hotness data. A valid unit count of operational memory cells is maintained on a block-by-block basis for a plurality of memory blocks. A hotness index count is also maintained based at least in part on the hotness data on a block-by-block basis for the plurality of memory blocks. One or more memory blocks of the plurality of memory blocks are selected for eviction from a single level cell region to an x-level cell region based at least in part on the valid unit count and the hotness index count.

公开(公告)号：US11119672B2

公开(公告)日：2021-09-14

申请号：US16532870

申请日：2019-08-06

Applicant: Intel Corporation

Inventor： Shankar Natarajan ,  Suresh Nagarajan ,  Shivashekar Muralishankar ,  Sriram Natarajan ,  Yihua Zhang

IPC: G06F12/00 ,  G06F3/06 ,  G11C11/56 ,  G06F12/02

Abstract: An embodiment of a memory controller device includes technology to control access to a memory array which includes a single-level cell region and a multi-level cell region, determine an amount of valid data in a dynamic portion of the single-level cell region at runtime, and adjust a size of the dynamic portion of the single-level cell region at runtime based on the determined amount of valid data in the dynamic portion of the single-level cell region. Other embodiments are disclosed and claimed.

公开(公告)号：US20200167089A1

公开(公告)日：2020-05-28

申请号：US16532870

申请日：2019-08-06

Applicant: Intel Corporation

Inventor： Shankar Natarajan ,  Suresh Nagarajan ,  Shivashekar Muralishankar ,  Sriram Natarajan ,  Yihua Zhang

IPC: G06F3/06 ,  G06F12/02 ,  G11C11/56

Abstract: An embodiment of a memory controller device includes technology to control access to a memory array which includes a single-level cell region and a multi-level cell region, determine an amount of valid data in a dynamic portion of the single-level cell region at runtime, and adjust a size of the dynamic portion of the single-level cell region at runtime based on the determined amount of valid data in the dynamic portion of the single-level cell region. Other embodiments are disclosed and claimed.