公开(公告)号：US12039329B2

公开(公告)日：2024-07-16

申请号：US17134108

申请日：2020-12-24

Applicant: Intel Corporation

Inventor： Wing Shek Wong ,  Vikash Agarwal ,  Charles Vitu ,  Mihir Shah

IPC: G06F9/24 ,  G06F9/22 ,  G06F9/30

CPC classification number: G06F9/223 ,  G06F9/30145

Abstract: Systems, methods, and apparatuses relating to circuitry to implement dynamic two-pass execution of a partial flag updating instruction in a processor are described. In one embodiment, a hardware processor core includes a decoder circuit to decode instructions into a set of one or more micro-operations, an execution circuit to execute the micro-operations decoded for the instructions, a data register to store data, a flag register to store a plurality of flags, and a reservation station circuit coupled between the decoder circuit and the execution circuit, the reservation station circuit to, in response to an indicator bit set to a multiple pass mode for a single micro-operation in a reservation station entry, perform a first dispatch of the single micro-operation to the execution circuit, when a source data operand in the data register is ready for execution and a source flag operand in the flag register is not ready for execution, to generate a data resultant, and a second dispatch of the single micro-operation to the execution circuit when both the source data operand in the data register and the source flag operand in the flag register are ready for execution to generate a flag resultant based on one or more of the plurality of flags in the flag register.

公开(公告)号：US20220011842A1

公开(公告)日：2022-01-13

申请号：US17484335

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Nagabhushan Reddy ,  Abhinay Gupta ,  Vinithra Janarthanan ,  Santhosh Raghuram Krishnaswamy ,  Pannerkumar Rajagopal ,  Siddharth Selvaraj ,  Mihir Shah ,  Vishwanath Somayaji

IPC: G06F1/30 ,  G06F1/3225 ,  G06F11/07

Abstract: An apparatus comprises a first circuitry to perform, in response to a first message from an operating system, a first process to place a computer device in a first operating mode, store state information in a volatile memory of the computer device, and start a timer for a time-out period for performing the first process. First components of the computer device are in a low power state. A second circuitry to detect, after the time-out period, a failure of the first process. A third circuitry to perform, in response to the detected failure of the first process, a second process to place the computer device in a second operating mode and store state information in a non-volatile memory of the computer device. The volatile memory is operational in the first operating mode and is in a low power state in the second operating mode.