公开(公告)号：US20230101725A1

公开(公告)日：2023-03-30

申请号：US17485167

申请日：2021-09-24

申请人： Intel Corporation

发明人： Debaleena NANDI ,  Mauro J. KOBRINSKY ,  Gilbert DEWEY ,  Chi-hing CHOI ,  Harold W. Kennel ,  Brian J. KRIST ,  Ashkar ALIYARUKUNJU ,  Cory BOMBERGER ,  Rushabh SHAH ,  Rishabh MEHANDRU ,  Stephen M. CEA ,  Chanaka MUNASINGHE ,  Anand S. MURTHY ,  Tahir GHANI

IPC分类号： H01L29/423 ,  H01L29/06 ,  H01L29/786

摘要： Gate-all-around integrated circuit structures having confined epitaxial source or drain structures, are described. For example, an integrated circuit structure includes a plurality of nanowires above a sub-fin. A gate stack is over the plurality of nanowires and the sub-fin. Epitaxial source or drain structures are on opposite ends of the plurality of nanowires. The epitaxial source or drain structures comprise germanium and boron, and a protective layer comprises silicon, and germanium that at least partially covers the epitaxial source or drain structures. A conductive contact comprising titanium silicide is on the epitaxial source or drain structures.