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1.
公开(公告)号:US20210408285A1
公开(公告)日:2021-12-30
申请号:US16913294
申请日:2020-06-26
Applicant: Intel Corporation
Inventor: Ryan HICKEY , Glenn A. GLASS , Anand S. MURTHY , Rushabh SHAH , Ju-Hyung NAM
IPC: H01L29/78 , H01L29/423 , H01L29/786
Abstract: Gate-all-around integrated circuit structures having germanium-doped nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having germanium-doped nanowire/nanoribbon channel structures, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a substrate. Individual ones of the vertical arrangement of nanowires have a relatively higher germanium concentration at a lateral mid-point of the nanowire than at lateral ends of the nanowire.
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公开(公告)号:US20230087399A1
公开(公告)日:2023-03-23
申请号:US17482880
申请日:2021-09-23
Applicant: Intel Corporation
Inventor: Debaleena NANDI , Cory BOMBERGER , Rushabh SHAH , Gilbert DEWEY , Nazila HARATIPOUR , Mauro J. KOBRINSKY , Anand S. MURTHY , Tahir GHANI
IPC: H01L27/088 , H01L29/06 , H01L29/417 , H01L29/423 , H01L29/66
Abstract: Gate-all-around integrated circuit structures having confined epitaxial source or drain structures, are described. For example, an integrated circuit structure includes a plurality of nanowires above a sub-fin. A gate stack is over the plurality of nanowires and the sub-fin. Epitaxial source or drain structures are on opposite ends of the plurality of nanowires. The epitaxial source or drain structures comprise i) a first PMOS epitaxial (pEPI) region of germanium and boron, ii) a second pEPI region of silicon, germanium and boron on the first pEPI region at a contact location, iii) a capping layer comprising silicon over the second pEPI region. A conductive contact material comprising titanium is on the capping layer.
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3.
公开(公告)号:US20220416050A1
公开(公告)日:2022-12-29
申请号:US17359327
申请日:2021-06-25
Applicant: Intel Corporation
Inventor: Debaleena NANDI , Cory BOMBERGER , Gilbert DEWEY , Anand S. MURTHY , Mauro KOBRINSKY , Rushabh SHAH , Chi-Hing CHOI , Harold W. KENNEL , Omair SAADAT , Adedapo A. ONI , Nazila HARATIPOUR , Tahir GHANI
IPC: H01L29/45 , H01L29/08 , H01L29/161 , H01L29/78 , H01L29/06 , H01L29/423 , H01L29/786
Abstract: Embodiments disclosed herein include semiconductor devices with improved contact resistances. In an embodiment, a semiconductor device comprises a semiconductor channel, a gate stack over the semiconductor channel, a source region on a first end of the semiconductor channel, a drain region on a second end of the semiconductor channel, and contacts over the source region and the drain region. In an embodiment, the contacts comprise a silicon germanium layer, an interface layer over the silicon germanium layer, and a titanium layer over the interface layer.
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公开(公告)号:US20230101725A1
公开(公告)日:2023-03-30
申请号:US17485167
申请日:2021-09-24
Applicant: Intel Corporation
Inventor: Debaleena NANDI , Mauro J. KOBRINSKY , Gilbert DEWEY , Chi-hing CHOI , Harold W. Kennel , Brian J. KRIST , Ashkar ALIYARUKUNJU , Cory BOMBERGER , Rushabh SHAH , Rishabh MEHANDRU , Stephen M. CEA , Chanaka MUNASINGHE , Anand S. MURTHY , Tahir GHANI
IPC: H01L29/423 , H01L29/06 , H01L29/786
Abstract: Gate-all-around integrated circuit structures having confined epitaxial source or drain structures, are described. For example, an integrated circuit structure includes a plurality of nanowires above a sub-fin. A gate stack is over the plurality of nanowires and the sub-fin. Epitaxial source or drain structures are on opposite ends of the plurality of nanowires. The epitaxial source or drain structures comprise germanium and boron, and a protective layer comprises silicon, and germanium that at least partially covers the epitaxial source or drain structures. A conductive contact comprising titanium silicide is on the epitaxial source or drain structures.
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公开(公告)号:US20220416043A1
公开(公告)日:2022-12-29
申请号:US17359422
申请日:2021-06-25
Applicant: Intel Corporation
Inventor: Cory BOMBERGER , Anand S. MURTHY , Rushabh SHAH , Kevin COOK , Anupama BOWONDER
IPC: H01L29/423 , H01L29/06 , H01L29/786 , H01L29/08 , H01L29/417
Abstract: Gate-all-around integrated circuit structures having confined epitaxial source or drain structures, are described. For example, an integrated circuit structure includes a plurality of nanowires above a sub-fin. A gate stack is over the plurality of nanowires and the sub-fin. Epitaxial source or drain structures are on opposite ends of the plurality of nanowires. The epitaxial source or drain structures comprise germanium and boron, and a protective layer comprising germanium, silicon and boron that at least partially covers the epitaxial source or drain structures to provide low contact resistivity.
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