公开(公告)号：US20190227749A1

公开(公告)日：2019-07-25

申请号：US16367638

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： Yogesh B. WAKCHAURE ,  Aliasgar S. MADRASWALA ,  David J. PELSTER ,  Donia SEBASTIAN ,  Curtis GITTENS ,  Xin GUO ,  Neelesh VEMULA ,  Varsha REGULAPATI ,  Naga Kiranmayee UPADHYAYULA

IPC: G06F3/06 ,  G11C16/04 ,  G11C16/26

Abstract: Independent multi-plane commands for non-volatile memory devices are described. In one example, a three-dimensional (3D) NAND memory device includes 3D NAND dies, each die including multiple planes of memory cells. The device includes input/output (I/O) circuitry to receive multiple commands from a host, each of the received commands to access one of the planes. The device includes logic (which can be implemented with, for example, an ASIC controller, firmware, or both) to queue the commands in separate queues for each of the planes based on a target plane of each of the commands. The logic issues the commands to their target planes independent of other planes' status, and tracks completion status of the commands independently for each plane.

公开(公告)号：US20190043593A1

公开(公告)日：2019-02-07

申请号：US15959538

申请日：2018-04-23

Applicant: Intel Corporation

Inventor： Xin GUO ,  Yu DU ,  Curtis GITTENS ,  David J. PELSTER ,  Donia SEBASTIAN

IPC: G11C16/30 ,  G11C16/26 ,  G11C16/32

Abstract: A reduction in Quality of Service (QoS) latency for host read commands in a power limited operation mode in a storage device is provided. A priority level is assigned to a host command using weighted round robin arbitration. Power resources are allocated based on the priority levels assigned to host commands to minimize host read command latency in the power limited operation mode.