公开(公告)号：US20180287630A1

公开(公告)日：2018-10-04

申请号：US15935117

申请日：2018-03-26

Applicant: INTEL CORPORATION

Inventor： VINODH GOPAL ,  JAMES D. GUILFORD ,  KIRK S. YAP ,  DANIEL F. CUTTER ,  WAJDI K. FEGHALI

IPC: H03M7/30 ,  H04L1/24

CPC classification number: H03M7/6041 ,  H03M7/3086 ,  H03M7/6005 ,  H03M7/6011 ,  H04L1/24

Abstract: Techniques and apparatus for verification of compressed data are described. In one embodiment, for example an apparatus to provide verification of compressed data may include at least one memory and logic, at least a portion of comprised in hardware coupled to the at least one memory, the logic to access compressed data, access compression information associated with the compressed data, decompress at least a portion of the compressed data to generate decompressed data, and verify the compressed data via a comparison of the decompressed data with the compression information. Other embodiments are described and claimed.

公开(公告)号：US20180183900A1

公开(公告)日：2018-06-28

申请号：US15390579

申请日：2016-12-26

Applicant: Intel Corporation

Inventor： JAMES D. GUILFORD ,  VINODH GOPAL ,  DANIEL F. CUTTER

IPC: H04L29/06

CPC classification number: H04L69/04 ,  H04L69/12

Abstract: In an embodiment, a processor comprises a plurality of processing cores and a compression accelerator to compress an input stream comprising a first data block and a second data block. The compression accelerator comprises a first compression engine to compress the first data block; and a second compression engine to update state data for the second compression engine using a sub-portion of the first data block; and after an update of the state data for the second compression engine using the sub-portion of the first data block, compress a second data block using the updated state data for the second compression engine. Other embodiments are described and claimed.

公开(公告)号：US20160173123A1

公开(公告)日：2016-06-16

申请号：US14571658

申请日：2014-12-16

Applicant: Intel Corporation

Inventor： VINODH GOPAL ,  JAMES D. GUILFORD ,  GILBERT M. WOLRICH ,  DANIEL F. CUTTER

IPC: H03M7/40 ,  H03M7/30

CPC classification number: H03M7/40 ,  H03M7/3086 ,  H03M7/6011

Abstract: In an embodiment, a processor includes a compression accelerator coupled to a plurality of hardware processing cores. The compression accelerator is to: receive input data to be compressed; select a particular intermediate format of a plurality of intermediate formats based on a type of compression software to be executed by at least one of the plurality of hardware processing cores; perform a duplicate string elimination operation on the input data to generate a partially compressed output in the particular intermediate format; and provide the partially compressed output in the particular intermediate format to the compression software, wherein the compression software is to perform an encoding operation on the partially compressed output to generate a final compressed output. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括耦合到多个硬件处理核心的压缩加速器。 压缩加速器是：接收要压缩的输入数据; 基于由所述多个硬件处理核心中的至少一个执行的压缩软件的类型，选择多个中间格式的特定中间格式; 对输入数据执行重复字符串消除操作，以产生特定中间格式的部分压缩输出; 并将特定中间格式的部分压缩的输出提供给压缩软件，其中压缩软件将对部分压缩的输出执行编码操作以产生最终的压缩输出。 描述和要求保护其他实施例。