公开(公告)号：US20180183900A1

公开(公告)日：2018-06-28

申请号：US15390579

申请日：2016-12-26

Applicant: Intel Corporation

Inventor： JAMES D. GUILFORD ,  VINODH GOPAL ,  DANIEL F. CUTTER

IPC: H04L29/06

CPC classification number: H04L69/04 ,  H04L69/12

Abstract: In an embodiment, a processor comprises a plurality of processing cores and a compression accelerator to compress an input stream comprising a first data block and a second data block. The compression accelerator comprises a first compression engine to compress the first data block; and a second compression engine to update state data for the second compression engine using a sub-portion of the first data block; and after an update of the state data for the second compression engine using the sub-portion of the first data block, compress a second data block using the updated state data for the second compression engine. Other embodiments are described and claimed.

公开(公告)号：US20160173123A1

公开(公告)日：2016-06-16

申请号：US14571658

申请日：2014-12-16

Applicant: Intel Corporation

Inventor： VINODH GOPAL ,  JAMES D. GUILFORD ,  GILBERT M. WOLRICH ,  DANIEL F. CUTTER

IPC: H03M7/40 ,  H03M7/30

CPC classification number: H03M7/40 ,  H03M7/3086 ,  H03M7/6011

Abstract: In an embodiment, a processor includes a compression accelerator coupled to a plurality of hardware processing cores. The compression accelerator is to: receive input data to be compressed; select a particular intermediate format of a plurality of intermediate formats based on a type of compression software to be executed by at least one of the plurality of hardware processing cores; perform a duplicate string elimination operation on the input data to generate a partially compressed output in the particular intermediate format; and provide the partially compressed output in the particular intermediate format to the compression software, wherein the compression software is to perform an encoding operation on the partially compressed output to generate a final compressed output. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括耦合到多个硬件处理核心的压缩加速器。 压缩加速器是：接收要压缩的输入数据; 基于由所述多个硬件处理核心中的至少一个执行的压缩软件的类型，选择多个中间格式的特定中间格式; 对输入数据执行重复字符串消除操作，以产生特定中间格式的部分压缩输出; 并将特定中间格式的部分压缩的输出提供给压缩软件，其中压缩软件将对部分压缩的输出执行编码操作以产生最终的压缩输出。 描述和要求保护其他实施例。

公开(公告)号：US20180287630A1

公开(公告)日：2018-10-04

申请号：US15935117

申请日：2018-03-26

Applicant: INTEL CORPORATION

Inventor： VINODH GOPAL ,  JAMES D. GUILFORD ,  KIRK S. YAP ,  DANIEL F. CUTTER ,  WAJDI K. FEGHALI

IPC: H03M7/30 ,  H04L1/24

CPC classification number: H03M7/6041 ,  H03M7/3086 ,  H03M7/6005 ,  H03M7/6011 ,  H04L1/24

Abstract: Techniques and apparatus for verification of compressed data are described. In one embodiment, for example an apparatus to provide verification of compressed data may include at least one memory and logic, at least a portion of comprised in hardware coupled to the at least one memory, the logic to access compressed data, access compression information associated with the compressed data, decompress at least a portion of the compressed data to generate decompressed data, and verify the compressed data via a comparison of the decompressed data with the compression information. Other embodiments are described and claimed.

公开(公告)号：US20160173126A1

公开(公告)日：2016-06-16

申请号：US15053921

申请日：2016-02-25

Applicant: INTEL CORPORATION

Inventor： JAMES D. GUILFORD ,  VINODH GOPAL ,  GILBERT M. WOLRICH ,  ERDING OZTURK ,  WAJDI K. FEGHALI

IPC: H03M7/30 ,  G06F9/30

CPC classification number: H03M7/60 ,  G06F9/30029 ,  H03M7/3068 ,  H03M7/6058

Abstract: An embodiment may include circuitry that may be capable of performing compression-related operations that may include: (a) indicating, at least in part, in a data structure at least one position of at least one subset of characters that are to be encoded as a symbol, (b) comparing, at least in part, at least one pair of multi-byte data words that are of identical predetermined fixed size, (c) maintaining, at least in part, an array of pointers to potentially matching strings that are to be compared with at least one currently examined string, and/or (d) allocating, at least in part, a first buffer portion to store at least one portion of uncompressed data from an application buffer that is to be input for compression to produce a compressed data stream. Other embodiments are described and claimed.

Abstract translation: 实施例可以包括可以执行压缩相关操作的电路，其可以包括：（a）至少部分地在数据结构中指示要被编码为的至少一个字符子集的至少一个位置 （b）至少部分比较至少一对具有相同预定固定大小的多字节数据字，（c）至少部分维持指向潜在匹配字符串的指针数组， 与至少一个当前检查的字符串进行比较，和/或（d）至少部分地分配第一缓冲器部分，以将来自要输入的压缩数据的至少一部分未压缩数据存储到要压缩的应用缓冲器中 产生压缩数据流。 描述和要求保护其他实施例。

公开(公告)号：US20180183462A1

公开(公告)日：2018-06-28

申请号：US15393190

申请日：2016-12-28

Applicant: INTEL CORPORATION

Inventor： VINODH GOPAL ,  JAMES D. GUILFORD

IPC: H03M7/40 ,  H03M7/30

CPC classification number: H03M7/40 ,  H03M7/02 ,  H03M7/30 ,  H03M7/3086 ,  H03M7/6023

Abstract: Techniques and apparatus for parallel decompression are described. In one embodiment, for example, an apparatus to provide parallel decompression may include at least one memory and logic for a decompression component, at least a portion of the logic comprised in hardware coupled to the at least one memory, the logic to determine decompression information of a compressed data unit, annotate the compressed data unit with at least a portion of the decompression information to generate an annotated data unit, parallel-decode the annotated data unit to generate a plurality of intermediate elements, and decode and merge the plurality of intermediate elements to generate a decompressed data unit. Other embodiments are described and claimed.

公开(公告)号：US20170060584A1

公开(公告)日：2017-03-02

申请号：US15257833

申请日：2016-09-06

Applicant: Intel Corporation

Inventor： GILBERT M. WOLRICH ,  KIRK S. YAP ,  JAMES D. GUILFORD ,  ERDINC OZTURK ,  VINODH GOPAL ,  WAJDI K. FEGHALI ,  SEAN M. GULLEY ,  MARTIN G. DIXON

IPC: G06F9/30

CPC classification number: G06F9/3016 ,  G06F7/525 ,  G06F7/57 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/3893

Abstract: An apparatus is described that includes a semiconductor chip having an instruction execution pipeline having one or more execution units with respective logic circuitry to: a) execute a first instruction that multiplies a first input operand and a second input operand and presents a lower portion of the result, where, the first and second input operands are respective elements of first and second input vectors; b) execute a second instruction that multiplies a first input operand and a second input operand and presents an upper portion of the result, where, the first and second input operands are respective elements of first and second input vectors; and, c) execute an add instruction where a carry term of the add instruction's adding is recorded in a mask register.

Abstract translation: 描述了一种装置，其包括具有指令执行流水线的半导体芯片，该指令执行流水线具有一个或多个具有相应逻辑电路的执行单元，以便：a）执行将第一输入操作数与第二输入操作数相乘并且呈现下一部分的第一指令 其中，第一和第二输入操作数是第一和第二输入向量的相应元素; b）执行第二指令，其将第一输入操作数和第二输入操作数相乘并呈现结果的上部，其中第一和第二输入操作数是第一和第二输入向量的相应元素; 以及c）执行加法指令，其中加法指令的相加的进位项被记录在掩码寄存器中。

公开(公告)号：US20160283159A1

公开(公告)日：2016-09-29

申请号：US14671929

申请日：2015-03-27

Applicant: Intel Corporation

Inventor： VINODH GOPAL ,  KIRK S. YAP ,  JAMES D. GUILFORD ,  JAWAD B. KHAN

IPC: G06F3/06 ,  G06F12/08 ,  H03M7/30

CPC classification number: G06F3/0638 ,  G06F3/061 ,  G06F3/0671 ,  G06F12/0875 ,  G06F12/0895 ,  G06F2212/401 ,  G06F2212/60 ,  H03M7/3086 ,  H03M7/3095 ,  H03M7/6058

Abstract: Compression and decompression technology within a solid-state device (SSD) is disclosed that provides a good compression ratio while taking up less on-chip area. An input interface receives an input stream to be compressed. An output interface provides a compressed stream. A history buffer is of a fixed size that is a fraction of a size of a data buffer. Processing logic encodes into the compressed stream element types, literals and pointers, the latter which reference copies of data found elsewhere within the history buffer during compression. The history buffer may be multiple banks in width, where the data is loaded from the input stream sequentially across rows of the banks. The decompression side may be similarly designed, optionally with a different number of banks. The pointers may be a fixed two bytes including four bits for length and eleven bits for offset of back reference to a copy (or other combination).

Abstract translation: 公开了在固态设备（SSD）中的压缩和解压缩技术，其提供了良好的压缩比，同时占用较少的片上区域。 输入接口接收要压缩的输入流。 输出接口提供压缩流。 历史缓冲区具有固定大小，它是数据缓冲区大小的一小部分。 处理逻辑编码为压缩流元素类型，文字和指针，后者在压缩期间引用历史缓冲区中其他位置的数据副本。 历史缓冲器可以是宽度的多个存储体，其中数据从输入流顺序地跨越存储体的行加载。 减压侧可以类似地设计，可选地具有不同数量的堤。 指针可以是固定的两个字节，包括用于长度的四个位和用于对拷贝（或其他组合）的反参考偏移的十一位）。

公开(公告)号：US20180095750A1

公开(公告)日：2018-04-05

申请号：US15282372

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： TRACY GARRETT DRYSDALE ,  VINODH GOPAL ,  JAMES D. GUILFORD

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/50 ,  G06F9/5044

Abstract: Methods and apparatuses relating to offload operations are described. In one embodiment, a hardware processor includes a core to execute a thread and offload an operation; and a first and second hardware accelerator to execute the operation, wherein the first and second hardware accelerator are coupled to shared buffers to store output data from the first hardware accelerator and provide the output data as input data to the second hardware accelerator, an input buffer descriptor array of the second hardware accelerator with an entry for each respective shared buffer, an input buffer response descriptor array of the second hardware accelerator with a corresponding response entry for each respective shared buffer, an output buffer descriptor array of the first hardware accelerator with an entry for each respective shared buffer, and an output buffer response descriptor array of the first hardware accelerator with a corresponding response entry for each respective shared buffer.

公开(公告)号：US20170235576A1

公开(公告)日：2017-08-17

申请号：US15371091

申请日：2016-12-06

Applicant: Intel Corporation

Inventor： SUDHIR K. SATPATHY ,  SANU K. MATHEW ,  VINODH GOPAL ,  JAMES D. GUILFORD

IPC: G06F9/30 ,  H03M7/30 ,  H03M7/40

CPC classification number: G06F9/30185 ,  G06F9/30021 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/30156 ,  G06F9/3016 ,  H03M7/4037 ,  H03M7/6005 ,  H03M7/6023

Abstract: An apparatus and method for performing parallel decoding of prefix codes such as Huffman codes. For example, one embodiment of an apparatus comprises: a first decompression module to perform a non-speculative decompression of a first portion of a prefix code payload comprising a first plurality of symbols; and a second decompression module to perform speculative decompression of a second portion of the prefix code payload comprising a second plurality of symbols concurrently with the non-speculative decompression performed by the first compression module.

公开(公告)号：US20160321076A1

公开(公告)日：2016-11-03

申请号：US14698486

申请日：2015-04-28

Applicant: Intel Corporation

Inventor： SUDHIR K. SATPATHY ,  SANU K. MATHEW ,  VINODH GOPAL ,  JAMES D. GUILFORD

IPC: G06F9/30

CPC classification number: G06F9/30185 ,  G06F9/30021 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/30156 ,  G06F9/3016 ,  H03M7/4037 ,  H03M7/6005 ,  H03M7/6023

Abstract: An apparatus and method for performing parallel decoding of prefix codes such as Huffman codes. For example, one embodiment of an apparatus comprises: a first decompression module to perform a non-speculative decompression of a first portion of a prefix code payload comprising a first plurality of symbols; and a second decompression module to perform speculative decompression of a second portion of the prefix code payload comprising a second plurality of symbols concurrently with the non-speculative decompression performed by the first compression module.

Abstract translation: 一种用于执行诸如霍夫曼码之类的前缀码的并行解码的装置和方法。 例如，装置的一个实施例包括：第一解压缩模块，用于执行包括第一多个符号的前缀码有效载荷的第一部分的非推测解压缩; 以及第二解压缩模块，用于执行与由第一压缩模块执行的非推测性解压缩同时地包括第二多个符号的前缀码有效载荷的第二部分的推测性解压缩。