公开(公告)号：US11544160B2

公开(公告)日：2023-01-03

申请号：US16456403

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Prashant D. Chaudhari ,  Michael N. Derr ,  Bradley Coffman ,  Arthur Jeremy Runyan ,  Gustavo Patricio Espinosa ,  Daniel James Knollmueller ,  Ivan Rodrigo Herrera Mejia

IPC: G06F11/16 ,  G06F13/42 ,  G06F11/07 ,  G06F1/04

Abstract: The systems and methods described herein provide the ability to detect a clocking element fault within an IC device and switch to an alternate clock. In response to detection of a fault in a phase-lock-loop (PLL) clocking element, the device may switch to an alternate clock so that error reporting logic can make forward progress on generating error message. The error message may be generated within an Intellectual Property (IP) cores (e.g., IP blocks), and may send the error message from the IP core to a system-on-a-chip (SOC), such as through an SOC Functional Safety (FuSA) error reporting infrastructure. In various examples, the clocking error may also be output to a hardware SOC pin, such as to provide a redundant path for error indication.