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公开(公告)号：US10749547B2
公开(公告)日：2020-08-18
申请号：US15938505
申请日：2018-03-28
Applicant: Intel Corporation
Inventor： Prashant D. Chaudhari , Michael N. Derr , Gustavo P. Espinosa , Daren J. Schmidt
Abstract: In embodiments, an apparatus may comprise random access memory (RAM); an error detecting and/or correcting code (EDCC) encoder to generate and add an error detecting and/or correcting code to a datum being written into the memory for storage; and an EDCC decoder to use the error detecting and/or correcting code added to the datum to correct one or more bits of error in the datum when the datum with the added error detecting and/or correcting code is read back from the RAM. Further, the apparatus may include an error detection and/or correction checker to inject one or more bits of error into the datum when the datum with the added error and/or correcting code is read back from the RAM, and check whether the EDCC decoder is able to correct the one or more bits of error injected into the datum.
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2.发明授权Sharing power between domains in a processor package using encoded power consumption information from a second domain to calculate an available power budget for a first domain 有权使用来自第二域的编码功耗信息来共享处理器包中的域之间的电力，以计算第一域的可用功率预算公开(公告)号：US09423858B2
公开(公告)日：2016-08-23
申请号：US13628172
申请日：2012-09-27
Applicant: Intel Corporation
Inventor： Xiuting C. Mann , Avinash Ananthakrishnan , Michael N. Derr , Craig Forbell
CPC classification number: G06F1/324 , G06F1/206 , G06F1/3206 , Y02D10/126 , Y02D10/16
Abstract: In an embodiment, the present invention includes a processor having a first domain with at least one core to execute instructions, a second domain coupled to the first domain and having at least one non-core circuit, and a power control unit (PCU) coupled to the first and second domains. The PCU may include a power sharing logic to receive encoded power consumption information from the second domain and to calculate an available power budget for the first domain based at least in part on the encoded power consumption information. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，本发明包括具有至少一个核的第一域以执行指令的处理器，耦合到第一域并具有至少一个非核心电路的第二域和耦合到第一域的功率控制单元（PCU） 到第一和第二个域。 PCU可以包括功率共享逻辑以从第二域接收编码的功耗信息，并且至少部分地基于编码的功耗信息来计算第一域的可用功率预算。 描述和要求保护其他实施例。
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公开(公告)号：US20230334613A1
公开(公告)日：2023-10-19
申请号：US18340139
申请日：2023-06-23
Applicant: Intel Corporation
Inventor： Kenneth Daxer , Stephen H. Gunther , Michael N. Derr , Eric Samson
Abstract: Described herein, in one embodiment, is a graphics processor comprising a plurality of dies integrated in a package, at least one die of the plurality of dies functionally heterogeneous relative to at least one other die of the plurality of dies and manufactured with a different process technology than the at least one other die.
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公开(公告)号：US11544160B2
公开(公告)日：2023-01-03
申请号：US16456403
申请日：2019-06-28
Applicant: Intel Corporation
Inventor： Prashant D. Chaudhari , Michael N. Derr , Bradley Coffman , Arthur Jeremy Runyan , Gustavo Patricio Espinosa , Daniel James Knollmueller , Ivan Rodrigo Herrera Mejia
Abstract: The systems and methods described herein provide the ability to detect a clocking element fault within an IC device and switch to an alternate clock. In response to detection of a fault in a phase-lock-loop (PLL) clocking element, the device may switch to an alternate clock so that error reporting logic can make forward progress on generating error message. The error message may be generated within an Intellectual Property (IP) cores (e.g., IP blocks), and may send the error message from the IP core to a system-on-a-chip (SOC), such as through an SOC Functional Safety (FuSA) error reporting infrastructure. In various examples, the clocking error may also be output to a hardware SOC pin, such as to provide a redundant path for error indication.
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公开(公告)号：US10387993B2
公开(公告)日：2019-08-20
申请号：US15721273
申请日：2017-09-29
Applicant: Intel Corporation
Inventor： Prashant D. Chaudhari , Michael N. Derr , Arthur J. Runyan
Abstract: Various techniques for providing a fault-tolerant graphics display engine are disclosed herein. In an example, a machine identifies a buffer under-run at a data buffer (DBUF) of a display engine. The machine adjusts a latency tolerance of the DBUF in response to identifying the buffer under-run. The machine determines that the buffer under-run at the DBUF persists after adjusting the latency tolerance. The machine determines whether a preset correction limit has been reached. If the preset correction limit has not been reached, the machine further adjusts the latency tolerance of the DBUF. If the preset correction limit has been reached, the machine removes, from a visual output associated with the display engine, one or more non-critical display assets.
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Patent Agency Ranking
公开(公告)号：US09189046B2
公开(公告)日：2015-11-17
申请号：US13783978
申请日：2013-03-04
Applicant: Intel Corporation
Inventor： Xiuting C. Man , Michael N. Derr , Jay D. Schwartz , Stephen H. Gunther , Jeremy J. Shrall , Shaun M. Conrad , Avinash N. Ananthakrishnan
CPC classification number: G06F1/32 , G06F1/206 , G06F1/3206 , G06F1/324 , Y02D10/126
Abstract: In an embodiment, a processor includes a first domain with at least one core to execute instructions and a second domain coupled to the first domain and including at least one non-core circuit. These domains can operate at independent frequencies, and a power control unit coupled to the domains may include a thermal logic to cause a reduction in a frequency of the first domain responsive to occurrence of a thermal event in the second domain. Other embodiments are described and claimed.
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公开(公告)号：US20190052286A1
公开(公告)日：2019-02-14
申请号：US15938505
申请日：2018-03-28
Applicant: Intel Corporation
Inventor： Prashant D. Chaudhari , Michael N. Derr , Gustavo P. Espinosa , Daren J. Schmidt
CPC classification number: H03M13/015 , B60W50/0205 , B60W2050/0005 , B60W2050/021 , G06F11/10 , G06F11/1068 , G06F11/2215 , G11C29/52 , G11C2029/0411 , H03M13/05
Abstract: In embodiments, an apparatus may comprise random access memory (RAM); an error detecting and/or correcting code (EDCC) encoder to generate and add an error detecting and/or correcting code to a datum being written into the memory for storage; and an EDCC decoder to use the error detecting and/or correcting code added to the datum to correct one or more bits of error in the datum when the datum with the added error detecting and/or correcting code is read back from the RAM. Further, the apparatus may include an error detection and/or correction checker to inject one or more bits of error into the datum when the datum with the added error and/or correcting code is read back from the RAM, and check whether the EDCC decoder is able to correct the one or more bits of error injected into the datum.
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公开(公告)号：US20160041595A1
公开(公告)日：2016-02-11
申请号：US14919780
申请日：2015-10-22
Applicant: Intel Corporation
Inventor： Barnes Cooper , Jeffrey R. Wilcox , Michael N. Derr , Neil W. Songer , Craig S. Forbell
IPC: G06F1/32
CPC classification number: G06F1/3206 , G06F1/3234 , G06F1/3243 , Y02D10/152
Abstract: In an embodiment, a processor includes a plurality of cores and power management logic. The power management logic may be to, in response to a first break event during a reduced power state in the processor, set an exit timer based on a platform latency tolerance, block a first plurality of break events from interrupting the reduced power state, and in response to a expiration of the exit timer, terminate the reduced power state. Other embodiments are described and claimed.
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公开(公告)号：US10678623B2
公开(公告)日：2020-06-09
申请号：US15818429
申请日：2017-11-20
Applicant: Intel Corporation
Inventor： Michael N. Derr , Balaji Vembu , Michael Mishaeli , Brent Chartrand , Bryan R White , Gustavo Espinosa , Prashant D. Chaudhari
Abstract: Various systems and methods for error handling are described herein. A system for error reporting and handling includes a common error handler that handles errors for a plurality of hardware devices, where the common error handler is operable with other parallel error reporting and handling mechanisms. The common error handler may be used to receive an error message from a hardware device, the error message related to an error; identify a source of the error message; identify a class of the error; identify an error definition of the error; determine whether the error requires a diagnostics operation as part of the error handling; initiate the diagnostics operation when the error requires the diagnostics operation; and clear the error at the hardware device.
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公开(公告)号：US20190051266A1
公开(公告)日：2019-02-14
申请号：US16139188
申请日：2018-09-24
Applicant: Intel Corporation
Inventor： Prashant D. Chaudhari , Michael N. Derr
Abstract: Technologies for end-to-end display integrity verification include a computing device with a display controller coupled to a display by a physical link. The computing device generates pixel data in a data buffer in memory, and the display controller outputs a pixel signal on the physical link based on the pixel data using a physical interface. The display receives the pixel signal and displays a corresponding image. A splicer is connected to the physical link and repeats the pixel signal to an I/O port of the computing device. The I/O port may be a USB Type-C port. The computing device compares pixel data received by the I/O port to the pixel data in the data buffer. The computing device may calculate checksums of the pixel data. If the pixel data does not match, the computing device may indicate a display integrity failure. Other embodiments are described and claimed.
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