公开(公告)号：US10318748B2

公开(公告)日：2019-06-11

申请号：US15283087

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： Neeraj S. Upasani ,  David P. Turley ,  Sergiu D. Ghetie ,  Zhangping Chen ,  Jason G. Sandri

IPC: G06F21/62 ,  G06F21/60 ,  G11C7/24 ,  G11C7/10 ,  G11C17/18 ,  G11C29/00

Abstract: Embodiments may be generally directed to techniques to encrypt and decrypt data in a first fuse block array using an encryption key of a second fuse block array, the second fuse block array having the encryption key comprising a plurality of segments of bits, an inverse encryption key comprising a second plurality of segments of bits, each segment of the inverse encryption key to correspond with a particular segment of the encryption key, and a random pattern having equally distributed bit values, the random pattern to enable detection of voltage attacks on the second fuse block array.

公开(公告)号：US10515218B2

公开(公告)日：2019-12-24

申请号：US15283381

申请日：2016-10-01

Applicant: Intel Corporation

Inventor： Sergiu D Ghetie ,  Neeraj S. Upasani ,  Sagar V. Dalvi ,  David P. Turley ,  Jeanne Guillory ,  Mark D. Chubb ,  Allen R. Wishman ,  Shahrokh Shahidzadeh

IPC: G06F21/57 ,  G06F21/72

Abstract: Embodiments detailed herein include, but are not limited to, a hardware processor to execute instructions and security circuitry to perform pre-boot operations including signature verification of a portion of firmware in a firmware storage hardware and initiating recovery upon a signature verification failure. The hardware processor comprises a plurality of cores in some embodiments. The hardware processor a multicore processor in some embodiments.

公开(公告)号：US11620398B2

公开(公告)日：2023-04-04

申请号：US16424558

申请日：2019-05-29

Applicant: INTEL CORPORATION

Inventor： Neeraj S. Upasani ,  David P. Turley ,  Sergiu D. Ghetie ,  Zhangping Chen ,  Jason G. Sandri

IPC: G06F21/62 ,  G06F21/60 ,  G11C7/24 ,  G11C7/10 ,  G11C17/18 ,  G11C29/00

Abstract: Embodiments may be generally directed to techniques to encrypt and decrypt data in a first fuse block array using an encryption key of a second fuse block array, the second fuse block array having the encryption key comprising a plurality of segments of bits, an inverse encryption key comprising a second plurality of segments of bits, each segment of the inverse encryption key to correspond with a particular segment of the encryption key, and a random pattern having equally distributed bit values, the random pattern to enable detection of voltage attacks on the second fuse block array.