公开(公告)号：US11023258B2

公开(公告)日：2021-06-01

申请号：US15396077

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Neeraj S. Upasani ,  Jeanne Guillory ,  Wojciech Powiertowski ,  Sergiu D Ghetie ,  Mohan J. Kumar ,  Murugasamy K. Nachimuthu

IPC: G06F9/445 ,  H04L12/24 ,  G06F15/78 ,  G06F9/4401 ,  H04L12/933 ,  G06F8/654

Abstract: Dynamically configurable server platforms and associated apparatus and methods. A server platform including a plurality of CPUs installed in respective sockets may be dynamically configured as multiple single-socket servers and as a multi-socket server. The CPUs are connected to a platform manager component comprising an SoC including one or more processors and an embedded FPGA. Following a platform reset, an FPGA image is loaded, dynamically configuring functional blocks and interfaces on the platform manager. The platform manager also includes pre-defined functional blocks and interfaces. During platform initialization the dynamically-configured functional blocks and interfaces are used to initialize the server platform, while both the pre-defined and dynamically-configured functional blocks and interfaces are used to support run-time operations. The server platform may be used in conventional rack architectures or implemented in a disaggregated rack architecture under which the single-socket and/or multi-socket servers are dynamically composed to employ disaggregated resources, such as memory, storage, and accelerators.

公开(公告)号：US10515218B2

公开(公告)日：2019-12-24

申请号：US15283381

申请日：2016-10-01

Applicant: Intel Corporation

Inventor： Sergiu D Ghetie ,  Neeraj S. Upasani ,  Sagar V. Dalvi ,  David P. Turley ,  Jeanne Guillory ,  Mark D. Chubb ,  Allen R. Wishman ,  Shahrokh Shahidzadeh

IPC: G06F21/57 ,  G06F21/72

Abstract: Embodiments detailed herein include, but are not limited to, a hardware processor to execute instructions and security circuitry to perform pre-boot operations including signature verification of a portion of firmware in a firmware storage hardware and initiating recovery upon a signature verification failure. The hardware processor comprises a plurality of cores in some embodiments. The hardware processor a multicore processor in some embodiments.