公开(公告)号：US10318748B2

公开(公告)日：2019-06-11

申请号：US15283087

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： Neeraj S. Upasani ,  David P. Turley ,  Sergiu D. Ghetie ,  Zhangping Chen ,  Jason G. Sandri

IPC: G06F21/62 ,  G06F21/60 ,  G11C7/24 ,  G11C7/10 ,  G11C17/18 ,  G11C29/00

Abstract: Embodiments may be generally directed to techniques to encrypt and decrypt data in a first fuse block array using an encryption key of a second fuse block array, the second fuse block array having the encryption key comprising a plurality of segments of bits, an inverse encryption key comprising a second plurality of segments of bits, each segment of the inverse encryption key to correspond with a particular segment of the encryption key, and a random pattern having equally distributed bit values, the random pattern to enable detection of voltage attacks on the second fuse block array.

公开(公告)号：US09472302B2

公开(公告)日：2016-10-18

申请号：US13788009

申请日：2013-03-07

Applicant: Intel Corporation

Inventor： Jason G. Sandri ,  Steve J. Brown ,  Peter R. Munguia ,  Monib Ahmed ,  Adrian R. Pearson

IPC: G11C17/18 ,  G11C17/16 ,  G11C8/20

CPC classification number: G11C17/18 ,  G11C8/20

Abstract: In accordance with some embodiments, fuse information may be written into a fuse array in a way that provides sufficient redundancy, making it harder for malicious parties to attack the fuse array.

Abstract translation: 根据一些实施例，熔丝信息可以以提供足够冗余的方式写入熔丝阵列，使得恶意方更难以攻击熔丝阵列。

公开(公告)号：US20180167199A1

公开(公告)日：2018-06-14

申请号：US15374700

申请日：2016-12-09

Applicant: Intel Corporation

Inventor： Himanshu Kaul ,  Sanu K. Mathew ,  Mark A. Anders ,  Jesse Walker ,  Jason G. Sandri

IPC: H04L9/06 ,  G06F12/14

CPC classification number: H04L9/0643 ,  G06F12/0862 ,  G06F12/1027 ,  G06F12/1408 ,  G06F17/50 ,  G06F2212/1052 ,  G06F2212/6026 ,  G09C1/00 ,  H04L9/0618 ,  H04L9/0625

Abstract: An instruction and logic for a Simon-based hashing for validation are described. In one embodiment, a processor comprises: a memory the memory to store a plurality of values; and a hash circuit comprising a Simon cipher circuit operable to receive the plurality of values from the memory, to apply a Simon cipher, and to generate an output for each of the plurality of values; and circuitry coupled to the Simon cipher circuit to combine outputs from the Simon cipher circuit for each value of the plurality of values into a hash digest that is indicative of whether the values in the memory are valid.

公开(公告)号：US08971137B2

公开(公告)日：2015-03-03

申请号：US13788020

申请日：2013-03-07

Applicant: Intel Corporation

Inventor： Jason G. Sandri ,  Ian S. Walker ,  Monib Ahmed

IPC: G11C17/16 ,  G11C29/04 ,  G11C11/418 ,  G11C17/18 ,  G11C29/02 ,  G11C29/00 ,  G11C29/44

CPC classification number: G11C29/04 ,  G11C11/418 ,  G11C17/16 ,  G11C17/18 ,  G11C29/02 ,  G11C29/785 ,  G11C29/787 ,  G11C2029/4402

Abstract: In accordance with some embodiments, instead of providing replacement rows, an area within a fuse array may be reserved for storing addresses of bits that are defective. Then these bits can be readily repaired by simply reading the stored state of identified defective bit, and inverting the stored state of the identified defective bit to get the correct output.

Abstract translation: 根据一些实施例，代替提供替换行，保险丝阵列内的区域可以被保留用于存储有缺陷的位的地址。 然后，通过简单地读出识别的有缺陷的位的存储状态，并且反转所识别的有缺陷位的存储状态以获得正确的输出，可以容易地修复这些位。

公开(公告)号：US08923030B2

公开(公告)日：2014-12-30

申请号：US13788051

申请日：2013-03-07

Applicant: Intel Corporation

Inventor： Jason G. Sandri ,  Ian S. Walker ,  Monib Ahmed

IPC: G11C17/00 ,  H01H85/04 ,  G06F21/70

CPC classification number: G06F21/70 ,  G06F21/79 ,  G11C17/16 ,  H01H85/04

Abstract: In one embodiment described herein, on-die programmable fuses may be used. On-die programmable fuses may be programmed by entities other than the chip manufacturer after the fuse array chip has been manufactured and shipped out. However, other non-volatile memories may also be used.

Abstract translation: 在本文所述的一个实施例中，可以使用片上可编程保险丝。 保险丝阵列芯片已经被制造和运出之后，片上可编程保险丝可以由除芯片制造商之外的实体编程。 然而，也可以使用其它非易失性存储器。

公开(公告)号：US09922720B2

公开(公告)日：2018-03-20

申请号：US13788028

申请日：2013-03-07

Applicant: Intel Corporation

Inventor： Jason G. Sandri ,  Horaira Abu ,  Charles A. Peterson ,  Matthew B. Pedersen ,  Brian Harris ,  Ian S. Walker ,  Monib Ahmed

IPC: G11C17/00 ,  G11C17/16 ,  G06F21/75 ,  G06F21/76 ,  G06F21/79 ,  G06F12/14 ,  G06F11/10 ,  G11C7/24 ,  G11C8/06 ,  G11C17/18 ,  G06F21/64 ,  G06F21/78 ,  G11C29/44

CPC classification number: G11C17/16 ,  G06F11/10 ,  G06F12/1408 ,  G06F21/64 ,  G06F21/75 ,  G06F21/755 ,  G06F21/76 ,  G06F21/78 ,  G06F21/79 ,  G11C7/24 ,  G11C8/06 ,  G11C17/18 ,  G11C2029/4402

Abstract: In accordance with some embodiments, the way in which the fuses are sensed and, particularly, their order may be made more random so that it is much more difficult to simply exercise the device and determine all the values of the storage elements within the fuse array. One result is a more secure storage device.

公开(公告)号：US09292713B2

公开(公告)日：2016-03-22

申请号：US13799553

申请日：2013-03-13

Applicant: Intel Corporation

Inventor： Jason G. Sandri ,  Monib Ahmed ,  Ian S. Walker

IPC: G06F21/76 ,  G06F21/10 ,  H04L9/32 ,  G06F21/85

CPC classification number: G06F21/76 ,  G06F21/10 ,  G06F21/85 ,  G06F2221/034 ,  H04L9/32

Abstract: In accordance with some embodiments, multiple blind debug passwords are provided. Each of a plurality of interested entities may have its own password and each password may unlock a specific set of features offered by an integrated circuit. In some embodiments each entity does not know the other passwords of the other entities. Potentially interested entities include an integrated circuit end customer, the original equipment manufacturer, the entity that provided the features to the integrated circuit and a conditional access provider. All debug features may be controlled solely via access to the debug tiers which are accessed by multiple debug passwords. Lower tier passwords are required in order to access higher tiers. Debug features may be separated into multiple tiers with more intrusive access requiring multiple debug passwords in order to gain access.

Abstract translation: 根据一些实施例，提供多个盲调试密码。 多个感兴趣的实体中的每一个可以具有其自己的密码，并且每个密码可以解锁由集成电路提供的特定的一组特征。 在一些实施例中，每个实体不知道其他实体的其他密码。 潜在感兴趣的实体包括集成电路终端客户，原始设备制造商，为集成电路提供特性的实体和条件接收提供商。 所有调试功能都可以通过访问由多个调试密码访问的调试层来控制。 为了访问较高级别，需要较低级别的密码。 调试功能可以分为多个层次，更多的入侵访问需要多个调试密码才能访问。

公开(公告)号：US11620398B2

公开(公告)日：2023-04-04

申请号：US16424558

申请日：2019-05-29

Applicant: INTEL CORPORATION

Inventor： Neeraj S. Upasani ,  David P. Turley ,  Sergiu D. Ghetie ,  Zhangping Chen ,  Jason G. Sandri

IPC: G06F21/62 ,  G06F21/60 ,  G11C7/24 ,  G11C7/10 ,  G11C17/18 ,  G11C29/00

Abstract: Embodiments may be generally directed to techniques to encrypt and decrypt data in a first fuse block array using an encryption key of a second fuse block array, the second fuse block array having the encryption key comprising a plurality of segments of bits, an inverse encryption key comprising a second plurality of segments of bits, each segment of the inverse encryption key to correspond with a particular segment of the encryption key, and a random pattern having equally distributed bit values, the random pattern to enable detection of voltage attacks on the second fuse block array.

公开(公告)号：US08799728B2

公开(公告)日：2014-08-05

申请号：US14063549

申请日：2013-10-25

Applicant: Intel Corporation

Inventor： Tina C. Zhong ,  Jason G. Sandri ,  Kenneth P. Griesser ,  Lori R. Borger

IPC: G01R31/28 ,  G06F13/00 ,  G01R31/26 ,  G01R31/3177 ,  G01R31/317 ,  G01R31/3185 ,  G01R31/319 ,  G06F11/25 ,  G06F11/36 ,  G06F11/30

CPC classification number: G01R31/3177 ,  G01R31/31705 ,  G01R31/318511 ,  G01R31/318513 ,  G01R31/319 ,  G06F11/079 ,  G06F11/25 ,  G06F11/3003 ,  G06F11/3089 ,  G06F11/364 ,  G06F11/3648

Abstract: In one embodiment, the present invention includes a semiconductor die such as a system on a chip (SoC) that includes a logic analyzer with a built-in trace buffer to store information communicated between on-die agents at speed and to provide the information to an off-die agent at a slower speed. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括诸如片上系统（SoC）的半导体管芯，其包括具有内置跟踪缓冲器的逻辑分析器，用于存储在速度上在管芯代理之间传送的信息，并将信息提供给 较低速度的脱模剂。 描述和要求保护其他实施例。

公开(公告)号：US08543776B2

公开(公告)日：2013-09-24

申请号：US13665198

申请日：2012-10-31

Applicant: Intel Corporation

Inventor： Tina C. Zhong ,  Jason G. Sandri ,  Kenneth P. Griesser ,  Lori R. Borger

IPC: G06F12/00 ,  G06F13/28 ,  G06F3/00 ,  G01R31/28

CPC classification number: G01R31/3177 ,  G01R31/31705 ,  G01R31/318511 ,  G01R31/318513 ,  G01R31/319 ,  G06F11/079 ,  G06F11/25 ,  G06F11/3003 ,  G06F11/3089 ,  G06F11/364 ,  G06F11/3648

Abstract: In one embodiment, the present invention includes a semiconductor die such as a system on a chip (SoC) that includes a logic analyzer with a built-in trace buffer to store information communicated between on-die agents at speed and to provide the information to an off-die agent at a slower speed. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括诸如片上系统（SoC）的半导体管芯，其包括具有内置跟踪缓冲器的逻辑分析器，用于存储在速度上在管芯代理之间传送的信息，并将信息提供给 较低速度的脱模剂。 描述和要求保护其他实施例。