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    REFERENCE VOLTAGE TRAINING PER PATH FOR HIGH SPEED MEMORY SIGNALING
    1.
    发明申请
    REFERENCE VOLTAGE TRAINING PER PATH FOR HIGH SPEED MEMORY SIGNALING 有权

    公开(公告)号：US20210326041A1

    公开(公告)日：2021-10-21

    申请号：US17359423

    申请日：2021-06-25

    Applicant: Intel Corporation

    Inventor： Arvind KUMAR ,  Dean-Dexter R. EUGENIO ,  John R. GOLES ,  Santhosh MUSKULA

    IPC: G06F3/06 ,  G06N20/00

    Abstract: In a memory system, reference voltage training per path provides the capability to train receiver and transmitter reference voltages to optimal values based on selected feedback per path from the memory device. Training receiver reference voltages to an optimal receiver reference voltage per path includes programming dedicated mode registers that enable a local receiver voltage reference adjuster circuit to adjust the receiver reference voltage per path to the optimal receiver reference voltage per path. Transmitter reference voltage training includes the capability to also train an optimal input timing delay for an optimal transmitter reference voltage. Reference voltage training can be performed by a host component and/or a test system having access to the selected feedback per path of the memory device undergoing training.

    UNIDIRECTIONAL INFORMATION CHANNEL TO MONITOR BIDIRECTIONAL INFORMATION CHANNEL DRIFT
    3.
    发明申请
    UNIDIRECTIONAL INFORMATION CHANNEL TO MONITOR BIDIRECTIONAL INFORMATION CHANNEL DRIFT 审中-公开

    公开(公告)号：US20200233821A1

    公开(公告)日：2020-07-23

    申请号：US16827205

    申请日：2020-03-23

    Applicant: Intel Corporation

    Inventor： Arvind KUMAR ,  Dean-Dexter R. EUGENIO ,  John R. GOLES

    IPC: G06F13/20 ,  G06F13/16

    Abstract: An N-bit bus includes (N−1) bidirectional interfaces to couple to (N−1) bidirectional signal lines to exchange (transmit and receive) signals between companion devices. The bus includes two unidirectional signal line interfaces. The first is a unidirectional receive interface to couple to a unidirectional signal line to receive signals from the companion device. The second is a unidirectional transmit interface to couple to a unidirectional signal line to transmit signals to the companion device. The bus provides N signal lines for the N-bit bus in each direction, with an additional “backwards facing” signal line. The backwards facing signal line can allow the devices to prepare for a switch in the direction of the N-bit bus.

    DUTY CYCLE ADJUSTER OPTIMIZATION TRAINING ALGORITHM TO MINIMIZE THE JITTER ASSOCIATED WITH DDR5 DRAM TRANSMITTER
    5.
    发明申请
    DUTY CYCLE ADJUSTER OPTIMIZATION TRAINING ALGORITHM TO MINIMIZE THE JITTER ASSOCIATED WITH DDR5 DRAM TRANSMITTER 有权

    公开(公告)号：US20210390991A1

    公开(公告)日：2021-12-16

    申请号：US17354788

    申请日：2021-06-22

    Applicant: Intel Corporation

    Inventor： Arvind KUMAR ,  Dean-Dexter R. EUGENIO ,  Santhosh MUSKULA

    IPC: G11C7/22 ,  G11C7/10 ,  G11C8/18 ,  H03K3/017 ,  H03K5/156

    Abstract: Methods and apparatus for duty cycle adjuster optimization training algorithms to minimize jitter associated with DDR5 DRAM transmitters. Basic and Advanced Duty Cycle Adjuster (DCA) training algorithms are implemented to reduce duty cycle error and hence reduce phase mismatch translated jitter in the transmitter DQS signals. In accordance with aspects of the Basic DCA training algorithm, duty cycles for QCLK, IBQCLK, and QBCLK are adjusted by a memory controller that utilizes a DCA function implemented on a memory module (e.g., DDR5 SDRAM DIMM) to obtain a first set of optimized DCA code settings. The first set of optimized DCA code settings are then used as initial settings for the Advance DCA training algorithm to further optimize the DCA code settings for QCLK, IBQCLK, and QBCLK. A similar technical may be employed to reduce duty cycle error and jitter for DQ signals.

    REFERENCE VOLTAGE ADJUSTMENT PER PATH FOR HIGH SPEED MEMORY SIGNALING
    6.
    发明申请
    REFERENCE VOLTAGE ADJUSTMENT PER PATH FOR HIGH SPEED MEMORY SIGNALING 有权

    公开(公告)号：US20210327524A1

    公开(公告)日：2021-10-21

    申请号：US17359442

    申请日：2021-06-25

    Applicant: Intel Corporation

    Inventor： Arvind KUMAR ,  Dean-Dexter R. EUGENIO ,  John R. GOLES

    IPC: G11C29/10 ,  G06N20/00 ,  G11C29/12

    Abstract: In a memory system, receiver reference voltage adjustment per path provides the capability to adjust receiver reference voltages on a per path basis. Adjustment of receiver reference voltages for the memory device to an optimal receiver reference voltage per path is accomplished with dedicated mode registers and a local receiver voltage reference adjuster circuit in the memory device for each data path. The optimal receiver reference voltage is determined during training based on selected feedback per path from the memory device. The dedicated mode registers contain adjustment values that were previously programmed during training, and include adjustments steps to add to or subtract from a global receiver reference voltage for all paths until reaching the optimal receiver reference voltage for a current path.

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