公开(公告)号：US09767026B2

公开(公告)日：2017-09-19

申请号：US13997437

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： Jose S. Niell ,  Daniel F. Cutter ,  James D. Allen ,  Deepak Limaye ,  Shadi T. Khasawneh

IPC: G06F12/08 ,  G06F12/10 ,  G06F12/0831 ,  G06F12/1027

CPC classification number: G06F12/0831 ,  G06F12/1027 ,  Y02D10/13

Abstract: In one embodiment, a conflict detection logic is configured to receive a plurality of memory requests from an arbiter of a coherent fabric of a system on a chip (SoC). The conflict detection logic includes snoop filter logic to downgrade a first snooped memory request for a first address to an unsnooped memory request when an indicator associated with the first address indicates that the coherent fabric has control of the first address. Other embodiments are described and claimed.

公开(公告)号：US09535860B2

公开(公告)日：2017-01-03

申请号：US13743795

申请日：2013-01-17

Applicant: Intel Corporation

Inventor： Daniel F. Cutter ,  Blaise Fanning ,  Ramadass Nagarajan ,  Jose S. Niell ,  Debra Bernstein ,  Deepak Limaye ,  Ioannis T. Schoinas ,  Ravishankar Iyer

IPC: G06F12/00 ,  G06F13/16

CPC classification number: G06F13/1663 ,  G06F13/1605 ,  G06F13/161 ,  G06F2212/1024 ,  G06F2213/0064 ,  Y02D10/14

Abstract: In an embodiment, a shared memory fabric is configured to receive memory requests from multiple agents, where at least some of the requests have an associated deadline value to indicate a maximum latency prior to completion of the memory request. Responsive to the requests, the fabric is to arbitrate between the requests based at least in part on the deadline values. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，共享存储器结构被配置为从多个代理接收存储器请求，其中至少一些请求具有关联的最终期限值，以在完成存储器请求之前指示最大等待时间。 响应于请求，结构是至少部分地基于期限值来在请求之间进行仲裁。 描述和要求保护其他实施例。

公开(公告)号：US20160092112A1

公开(公告)日：2016-03-31

申请号：US14496300

申请日：2014-09-25

Applicant: Intel Corporation

Inventor： Hasmet Akgun ,  Premkishore Shivakumar ,  Deepak Limaye

IPC: G06F3/06

CPC classification number: G06F9/44 ,  G06F3/06 ,  H03M5/00 ,  H03M7/30 ,  H03M7/3079

Abstract: An apparatus includes a controller and a compression unit. The controller includes logic to receive an input line of data from a data producer and divide the input line of data into a plurality of segment. Each segment corresponds to a compression context and to a multi-line data tile. The controller also includes logic to write a first segment of the input line to a first multi-line data tile, and to write a second segment of the input line to a second multi-line data tile upon reaching a boundary of the first multi-line data tile. The compression unit includes logic to apply a first compression context to the first multi-line data tile and a second compression context to the second multi-line data tile.

Abstract translation: 一种装置包括控制器和压缩单元。 控制器包括从数据生成器接收数据的输入行并将输入数据线划分成多个段的逻辑。 每个段对应于压缩上下文和多行数据块。 控制器还包括将输入线的第一段写入第一多行数据块的逻辑，并且在到达第一多行数据块的边界时将输入线的第二段写入第二多行数据块， 线数据瓦片。 压缩单元包括将第一压缩上下文应用于第一多行数据块的逻辑，以及将第二压缩上下文应用于第二多行数据块。