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    BIT CHECK PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS TO CHECK A BIT WITH AN INDICATED CHECK BIT VALUE
    1.
    发明申请
    BIT CHECK PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS TO CHECK A BIT WITH AN INDICATED CHECK BIT VALUE 审中-公开

    公开(公告)号：US20180004655A1

    公开(公告)日：2018-01-04

    申请号：US15201303

    申请日：2016-07-01

    Applicant: Intel Corporation

    Inventor： Hugh Wilkinson ,  William R. Wheeler ,  Debra Bernstein

    IPC: G06F12/02 ,  G11C7/10

    Abstract: A processor of an aspect includes a register to store a condition code bit, and a decode unit to decode a bit check instruction. The bit check instruction is to indicate a first source operand that is to include a first bit, and is to indicate a check bit value for the first bit. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the bit check instruction, is to compare the first bit with the check bit value, and update a condition code bit to indicate whether the first bit equals or does not equal the check bit value. Other processors, methods, systems, and instructions are disclosed.

    ACCELERATOR FABRIC FOR DISCRETE GRAPHICS
    6.
    发明申请
    ACCELERATOR FABRIC FOR DISCRETE GRAPHICS 有权

    公开(公告)号：US20220113967A1

    公开(公告)日：2022-04-14

    申请号：US17561197

    申请日：2021-12-23

    Applicant: Intel Corporation

    Inventor： Abhishek Reddy Pamu ,  Lakshminarayana Pappu ,  David J. Harriman ,  Debra Bernstein ,  Ramadass Nagarajan

    IPC: G06F9/30 ,  G06T1/20 ,  G06T1/60

    Abstract: A system comprising a discrete graphics system-on-chip (SoC) to couple to a host processor unit, the SoC comprising a fabric comprising a handler circuitry to decode a request from a compute engine, the handler circuitry to route the request based on an opcode included in the request, the handler configured to decode the opcode from a set of opcodes for use in requests by the compute engine, wherein the set of opcodes include opcodes corresponding to a first write request type and a first read request type, wherein requests of the first write request type and the first read request type are routed to either the host memory or the graphics memory; and a second write request type and a second read request type, wherein requests of the second write request type and the second request type are to be routed to the sideband network.

    Techniques for processor queue management
    10.
    发明授权
    Techniques for processor queue management 有权

    公开(公告)号：US11134021B2

    公开(公告)日：2021-09-28

    申请号：US15394488

    申请日：2016-12-29

    Applicant: INTEL CORPORATION

    Inventor： Jonathan Kenny ,  Niall D. McDonnell ,  Andrew Cunningham ,  Debra Bernstein ,  William G. Burroughs ,  Hugh Wilkinson

    IPC: H04L12/863 ,  G06F13/00 ,  H04L12/801

    Abstract: Techniques and apparatus for processor queue management are described. In one embodiment, for example, an apparatus to provide queue congestion management assistance may include at least one memory and logic for a queue manager, at least a portion of the logic comprised in hardware coupled to the at least one memory, the logic to determine queue information for at least one queue element (QE) queue storing at least one QE, compare the queue information to at least one queue threshold value, and generate a queue notification responsive to the queue information being outside of the queue threshold value. Other embodiments are described and claimed.

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