公开(公告)号：US20240004310A1

公开(公告)日：2024-01-04

申请号：US17854799

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： William Blanton ,  Deepak Selvanathan ,  Shakul Tandon ,  Martin N. Weiss

IPC: G03F7/20 ,  H01L23/544

CPC classification number: G03F7/70633 ,  H01L23/544

Abstract: Embodiments disclosed herein include semiconductor die with overlay marks, electronic devices that include semiconductor dies with overlay marks, and methods of measuring overlay. In one embodiment, a semiconductor die includes multiple overlay marks, including a first overlay mark and a second overlay mark. The first overlay mark is at a first position on the semiconductor die and includes a first set of patterns with a first orientation. The second overlay mark is at a second position on the semiconductor die and includes a second set of patterns with a second orientation. The first position of the first mark and the second position of the second mark are non-overlapping. In addition, the first orientation of the patterns in the first mark is substantially orthogonal to the second orientation of the patterns in the second mark.