公开(公告)号：US10338474B2

公开(公告)日：2019-07-02

申请号：US15528329

申请日：2015-06-18

Applicant: Intel Corporation

Inventor： Shakul Tandon ,  Yan A. Borodovsky ,  Charles H. Wallace ,  Paul A. Nyhus

IPC: G03F7/09 ,  G03F7/11 ,  G03F7/20 ,  H01L21/027 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/8234

Abstract: Lithographic apparatuses suitable for, and methodologies involving, complementary e-beam lithography (CEBL) are described. Particular embodiments are directed to implementation of an underlying absorbing and/or conducting layer for ebeam direct write (EBDW) lithography.

公开(公告)号：US11107658B2

公开(公告)日：2021-08-31

申请号：US16323128

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Shakul Tandon ,  Mark C. Phillips ,  Shem O. Ogadhoh ,  John A. Swanson

IPC: H01J37/317 ,  H01L21/033 ,  H01J37/30 ,  H01L21/027 ,  H01J37/04

Abstract: Lithographic apparatuses suitable for complementary e-beam lithography (CEBL) are described. In an example, a method of forming a pattern for a semiconductor structure includes forming a pattern of parallel lines above a substrate. The method also includes aligning the substrate in an e-beam tool to provide the pattern of parallel lines parallel with a scan direction of the e-beam tool. The e-beam tool includes a column having a blanker aperture array (BAA) with a staggered pair of columns of openings along an array direction orthogonal to the scan direction. The method also includes forming a pattern of cuts or vias in or above the pattern of parallel lines to provide line breaks for the pattern of parallel lines by scanning the substrate along the scan direction. A cumulative current through the column has a non-zero and substantially uniform cumulative current value throughout the scanning.

公开(公告)号：US10395883B2

公开(公告)日：2019-08-27

申请号：US16069708

申请日：2016-03-31

Applicant: Intel Corporation

Inventor： Shakul Tandon ,  Mark C. Phillips ,  Gabriele Canzi

IPC: H01J37/20 ,  H01J37/04 ,  H01J37/147 ,  H01J37/317 ,  H01J37/302 ,  H01L21/027 ,  H01L21/768

Abstract: Lithographic apparatuses suitable for complementary e-beam lithography (CEBL) are described. In an example, a blanker aperture array (BAA) for an e-beam tool includes a first column of openings along a first direction and having a pitch. Each opening of the first column of openings has a dimension in the first direction. The BAA also includes a second column of openings along the first direction and staggered from the first column of openings. The second column of openings has the pitch. Each opening of the second column of openings has the dimension in the first direction. A scan direction of the BAA is along a second direction orthogonal to the first direction. The openings of the first column of openings overlap with the openings of the second column of openings by at least 5% but less than 50% of the dimension in the first direction when scanned along the second direction.

公开(公告)号：US20240004310A1

公开(公告)日：2024-01-04

申请号：US17854799

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： William Blanton ,  Deepak Selvanathan ,  Shakul Tandon ,  Martin N. Weiss

IPC: G03F7/20 ,  H01L23/544

CPC classification number: G03F7/70633 ,  H01L23/544

Abstract: Embodiments disclosed herein include semiconductor die with overlay marks, electronic devices that include semiconductor dies with overlay marks, and methods of measuring overlay. In one embodiment, a semiconductor die includes multiple overlay marks, including a first overlay mark and a second overlay mark. The first overlay mark is at a first position on the semiconductor die and includes a first set of patterns with a first orientation. The second overlay mark is at a second position on the semiconductor die and includes a second set of patterns with a second orientation. The first position of the first mark and the second position of the second mark are non-overlapping. In addition, the first orientation of the patterns in the first mark is substantially orthogonal to the second orientation of the patterns in the second mark.

公开(公告)号：US11581162B2

公开(公告)日：2023-02-14

申请号：US17388945

申请日：2021-07-29

Applicant: Intel Corporation

Inventor： Shakul Tandon ,  Mark C. Phillips ,  Shem O. Ogadhoh ,  John A. Swanson

IPC: H01J37/30 ,  H01J37/317 ,  H01L21/027 ,  H01J37/04 ,  H01L21/033

Abstract: Lithographic apparatuses suitable for complementary e-beam lithography (CEBL) are described. In an example, a method of forming a pattern for a semiconductor structure includes forming a pattern of parallel lines above a substrate. The method also includes aligning the substrate in an e-beam tool to provide the pattern of parallel lines parallel with a scan direction of the e-beam tool. The e-beam tool includes a column having a blanker aperture array (BAA) with a staggered pair of columns of openings along an array direction orthogonal to the scan direction. The method also includes forming a pattern of cuts or vias in or above the pattern of parallel lines to provide line breaks for the pattern of parallel lines by scanning the substrate along the scan direction. A cumulative current through the column has a non-zero and substantially uniform cumulative current value throughout the scanning.

公开(公告)号：US20240321660A1

公开(公告)日：2024-09-26

申请号：US18188577

申请日：2023-03-23

Applicant: Intel Corporation

Inventor： Shakul Tandon

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  H01L23/532 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L23/3107 ,  H01L21/56 ,  H01L23/49827 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/53257 ,  H01L24/16 ,  H01L25/0652 ,  H01L25/105 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/182

Abstract: Embodiments of semiconductor devices with stitched guard rings, along with methods and lithographic reticles for forming the same, are disclosed herein. In one example, a semiconductor die includes a substrate with integrated circuitry, and a guard ring surrounding the integrated circuitry. The guard ring includes traces arranged in a pattern of lines and rungs, where the lines extend around the integrated circuitry and the rungs extend crosswise between at least some of the lines.

公开(公告)号：US20230194997A1

公开(公告)日：2023-06-22

申请号：US17558417

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Mark Phillips ,  Shakul Tandon

IPC: G03F7/20

CPC classification number: G03F7/70633 ,  G03F7/70475 ,  G03F7/70741 ,  G03F7/70466

Abstract: Reticles, line feature patterns, and methods are described related to improving overlay margins in reticle stitching applications. A first reticle to expose a first field includes a first portion of a line feature. The first portion has a pattern inclusive of one or more pattern features. The first reticle or a second reticle to expose a second field adjacent the first filed includes a second portion of the line feature. The second portion has an inverse pattern relative to the first pattern such that, when the first and inverse patterns are overlaid, a continuous merged region is formed.