公开(公告)号：US20190042292A1

公开(公告)日：2019-02-07

申请号：US15904371

申请日：2018-02-25

Applicant: Intel Corporation

Inventor： Stephen T. Palermo ,  Gerald Rogers ,  Shih-Wei Roger Chien ,  Namakkal Venkatesan ,  Rajesh Gadiyar

IPC: G06F9/455 ,  G06F13/40

Abstract: Technologies for application-specific network acceleration include a computing device including a processor and an accelerator device such as a field-programmable gate array (FPGA). The processor and the accelerator device are coupled via a coherent interconnect and may be included in a multi-chip package. The computing device binds a virtual machine executed by the processor with an application function unit of the accelerator device via the coherent interconnect. The computing device processes network application data with the virtual machine and the application function unit within a coherency domain maintained with the coherent interconnect. Processing the network data may include processing a packet of a network flow by the virtual machine and processing subsequent packets of the network flow by the application function unit. Other embodiments are described and claimed.

公开(公告)号：US20190034363A1

公开(公告)日：2019-01-31

申请号：US15853670

申请日：2017-12-22

Applicant: Intel Corporation

Inventor： Stephen Palermo ,  Gerald Rogers ,  Shih-Wei Chien ,  Namakkal Venkatesan

IPC: G06F13/16 ,  G06F9/455 ,  G06F13/40 ,  G06F13/42 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0875

Abstract: A computer system may comprise a multi-chip package (MCP), which includes multi-core processor circuitry and hardware accelerator circuitry. The multi-core processor circuitry may comprise a plurality of processing cores, and the hardware accelerator circuitry may be coupled with the multi-core processor circuitry via one or more coherent interconnects and one or more non-coherent interconnects. A coherency domain of the MCP may be extended to encompass the hardware accelerator circuitry, or portions thereof An interconnect selection module may select an individual coherent interconnect or an individual non-coherent interconnect based on application requirements of an application to be executed and a workload characteristic policy. Other embodiments are described and/or claimed.

公开(公告)号：US20220197685A1

公开(公告)日：2022-06-23

申请号：US17392861

申请日：2021-08-03

Applicant: Intel Corporation

Inventor： Stephen T. Palermo ,  Gerald Rogers ,  Shih-Wei Roger Chien ,  Namakkal Venkatesan ,  Rajesh Gadiyar

IPC: G06F9/455 ,  G06F13/16 ,  G06F13/40 ,  G06F13/42 ,  G06F12/0815 ,  G06F12/0875 ,  G06F12/0811 ,  G06F9/50 ,  G06F9/38

Abstract: Technologies for application-specific network acceleration include a computing device including a processor and an accelerator device such as a field-programmable gate array (FPGA). The processor and the accelerator device are coupled via a coherent interconnect and may be included in a multi-chip package. The computing device binds a virtual machine executed by the processor with an application function unit of the accelerator device via the coherent interconnect. The computing device processes network application data with the virtual machine and the application function unit within a coherency domain maintained with the coherent interconnect. Processing the network data may include processing a packet of a network flow by the virtual machine and processing subsequent packets of the network flow by the application function unit. Other embodiments are described and claimed.

公开(公告)号：US11086650B2

公开(公告)日：2021-08-10

申请号：US15904371

申请日：2018-02-25

Applicant: Intel Corporation

Inventor： Stephen T. Palermo ,  Gerald Rogers ,  Shih-Wei Roger Chien ,  Namakkal Venkatesan ,  Rajesh Gadiyar

IPC: G06F9/455 ,  G06F13/16 ,  G06F13/40 ,  G06F13/42 ,  G06F12/0815 ,  G06F12/0875 ,  G06F12/0811 ,  G06F9/50 ,  G06F9/38

Abstract: Technologies for application-specific network acceleration include a computing device including a processor and an accelerator device such as a field-programmable gate array (FPGA). The processor and the accelerator device are coupled via a coherent interconnect and may be included in a multi-chip package. The computing device binds a virtual machine executed by the processor with an application function unit of the accelerator device via the coherent interconnect. The computing device processes network application data with the virtual machine and the application function unit within a coherency domain maintained with the coherent interconnect. Processing the network data may include processing a packet of a network flow by the virtual machine and processing subsequent packets of the network flow by the application function unit. Other embodiments are described and claimed.

公开(公告)号：US11249779B2

公开(公告)日：2022-02-15

申请号：US15853670

申请日：2017-12-22

Applicant: Intel Corporation

Inventor： Stephen Palermo ,  Gerald Rogers ,  Shih-Wei Chien ,  Namakkal Venkatesan

IPC: G06F9/455 ,  G06F13/16 ,  G06F13/40 ,  G06F13/42 ,  G06F12/0815 ,  G06F12/0875 ,  G06F12/0811 ,  G06F9/50 ,  G06F9/38

Abstract: A computer system may comprise a multi-chip package (MCP), which includes multi-core processor circuitry and hardware accelerator circuitry. The multi-core processor circuitry may comprise a plurality of processing cores, and the hardware accelerator circuitry may be coupled with the multi-core processor circuitry via one or more coherent interconnects and one or more non-coherent interconnects. A coherency domain of the MCP may be extended to encompass the hardware accelerator circuitry, or portions thereof An interconnect selection module may select an individual coherent interconnect or an individual non-coherent interconnect based on application requirements of an application to be executed and a workload characteristic policy. Other embodiments are described and/or claimed.