公开(公告)号：US20220182215A1

公开(公告)日：2022-06-09

申请号：US17677467

申请日：2022-02-22

Applicant: Intel Corporation

Inventor： Ehud Shoor ,  Tsion Vidal ,  Uri Hermoni ,  Efraim Kugman ,  Sarel Wechsler ,  Oren Salomon ,  Golan Cohen

IPC: H04L7/027 ,  H04L7/00

Abstract: In one embodiment, an apparatus comprises: a receiver to receive training data from a transmitter; a clock and data recovery (CDR) circuit coupled to the receiver, the CDR circuit to recover a recovered clock signal from the training data; and a media access control (MAC) circuit coupled to the CDR circuit, wherein the MAC circuit is to send a clock switch indicator to the CDR circuit to cause the CDR circuit to halt tracking operation of the CDR circuit. Other embodiments are described and claimed.

公开(公告)号：US20220345289A1

公开(公告)日：2022-10-27

申请号：US17858692

申请日：2022-07-06

Applicant: Intel Corporation

Inventor： Ehud Shoor ,  Tsion Vidal ,  Vladislav Kopzon ,  Uri Hermoni ,  Golan Cohen ,  Efraim Kugman ,  Ziv Kabiry

IPC: H04L7/033

Abstract: The circuits and methods described herein provide technical solutions for technical problems facing USB links. To reduce or eliminate effects associated with a USB link entering a low-power mode, initial link acquisition may be performed while the spread-spectrum-clocking (SSC) modulation is disabled. Following the initial link acquisition, the SSC modulation may be enabled dynamically in a later stage. This delayed enablement of the re-timers provides improved performance over solutions in which the SSC modulation is constantly enabled, including reducing the complexity of the timing training process and enabling a faster USB link re-establishment. This reduced link acquisition period may enable the system to enter power saving modes more frequently, and may reduce latency involved in exiting power saving modes. This may maintain or improve total USB transmission speeds and may reduce USB-related power consumption for USB connected devices.