公开(公告)号：US08711018B2

公开(公告)日：2014-04-29

申请号：US13781039

申请日：2013-02-28

申请人： Intel Corporation

发明人： Ehud Shoor ,  Dror Lazar ,  Assaf Benhamou

IPC分类号： H03M9/00

CPC分类号： H03M9/00 ,  H04J3/0608

摘要： In one embodiment, the present invention includes a de-serializer to receive serial data at a first rate and to output a parallel data frame corresponding to the serial data aligned to a frame alignment boundary in response to a phase control signal received from a feedback loop coupled between the de-serializer and a receiver logic coupled to an output of the de-serializer. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括解串器，用于以第一速率接收串行数据，并响应于从反馈回路接收到的相位控制信号，输出对应于与帧对准边界对准的串行数据的并行数据帧 耦合在解串器和耦合到解串器的输出的接收器逻辑之间。 描述和要求保护其他实施例。

公开(公告)号：US20220345289A1

公开(公告)日：2022-10-27

申请号：US17858692

申请日：2022-07-06

申请人： Intel Corporation

发明人： Ehud Shoor ,  Tsion Vidal ,  Vladislav Kopzon ,  Uri Hermoni ,  Golan Cohen ,  Efraim Kugman ,  Ziv Kabiry

IPC分类号： H04L7/033

摘要： The circuits and methods described herein provide technical solutions for technical problems facing USB links. To reduce or eliminate effects associated with a USB link entering a low-power mode, initial link acquisition may be performed while the spread-spectrum-clocking (SSC) modulation is disabled. Following the initial link acquisition, the SSC modulation may be enabled dynamically in a later stage. This delayed enablement of the re-timers provides improved performance over solutions in which the SSC modulation is constantly enabled, including reducing the complexity of the timing training process and enabling a faster USB link re-establishment. This reduced link acquisition period may enable the system to enter power saving modes more frequently, and may reduce latency involved in exiting power saving modes. This may maintain or improve total USB transmission speeds and may reduce USB-related power consumption for USB connected devices.

公开(公告)号：US20220182215A1

公开(公告)日：2022-06-09

申请号：US17677467

申请日：2022-02-22

申请人： Intel Corporation

发明人： Ehud Shoor ,  Tsion Vidal ,  Uri Hermoni ,  Efraim Kugman ,  Sarel Wechsler ,  Oren Salomon ,  Golan Cohen

IPC分类号： H04L7/027 ,  H04L7/00

摘要： In one embodiment, an apparatus comprises: a receiver to receive training data from a transmitter; a clock and data recovery (CDR) circuit coupled to the receiver, the CDR circuit to recover a recovered clock signal from the training data; and a media access control (MAC) circuit coupled to the CDR circuit, wherein the MAC circuit is to send a clock switch indicator to the CDR circuit to cause the CDR circuit to halt tracking operation of the CDR circuit. Other embodiments are described and claimed.