公开(公告)号：US20190101961A1

公开(公告)日：2019-04-04

申请号：US15720484

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Kemal Aygun ,  Zhichao Zhang ,  Cemil Geyik ,  Guneet Kaur

IPC: G06F1/18 ,  H05K7/14 ,  H01R13/10 ,  H05K3/40

Abstract: Methods/structures of forming package structures are described. Those methods/structures may include a conductive pin comprising: a cantilever beam portion physically coupled with a first side of a package substrate; a contact pin portion, wherein a terminal end of the contact pin portion is physically and electrically coupled to a board; a housing structure comprising a housing cavity, wherein the contact pin portion is disposed at least partially within the housing cavity; and a conductive material disposed on housing sides and/or adjacent a surface of the housing cavity. The placement of the conductive material is optimized to meet the requirements for either double data rate (DDR) and/or peripheral component interface express (PCIe) interfaces.

公开(公告)号：US10303225B2

公开(公告)日：2019-05-28

申请号：US15720484

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Kemal Aygun ,  Zhichao Zhang ,  Cemil Geyik ,  Guneet Kaur

IPC: H01L23/02 ,  G06F1/18 ,  H05K3/40 ,  H01R13/10 ,  H05K7/14

Abstract: Methods/structures of forming package structures are described. Those methods/structures may include a conductive pin comprising: a cantilever beam portion physically coupled with a first side of a package substrate; a contact pin portion, wherein a terminal end of the contact pin portion is physically and electrically coupled to a board; a housing structure comprising a housing cavity, wherein the contact pin portion is disposed at least partially within the housing cavity; and a conductive material disposed on housing sides and/or adjacent a surface of the housing cavity. The placement of the conductive material is optimized to meet the requirements for either double data rate (DDR) and/or peripheral component interface express (PCIe) interfaces.