公开(公告)号：US11862547B2

公开(公告)日：2024-01-02

申请号：US16804516

申请日：2020-02-28

Applicant: Intel Corporation

Inventor： Zhichao Zhang ,  Zhe Chen ,  Srikant Nekkanty ,  Sriram Srinivasan

IPC: H01L23/498 ,  H01L23/538 ,  H01L23/58

CPC classification number: H01L23/49838 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/58

Abstract: Embodiments include assemblies. An assembly includes a substrate having a first interconnect and a second interconnect. The first interconnect has a first conductive pad and a second conductive pad, and the second interconnect has a third conductive pad and a fourth conductive pad. The assembly includes a socket over the substrate. The socket has a first pin, a second pin, and a base layer with a first pad and a second pad. The first and second pins are vertically over the respective first and second interconnects. The first pad is directly coupled to the first pin and fourth conductive pad, while the second pad is directly coupled to the second pin and second conductive pad. The first pad is positioned partially within a footprint of the third conductive pad, and the second pad is positioned partially within a footprint of the first conductive pad.

公开(公告)号：US20230420347A1

公开(公告)日：2023-12-28

申请号：US17847282

申请日：2022-06-23

Applicant: Intel Corporation

Inventor： Cemil Geyik ,  Zhiguo Qian ,  Kristof Kuwawi Darmawikarta ,  Zhichao Zhang ,  Kemal Aygun

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L21/4857 ,  H01L25/0652

Abstract: Embodiments of a microelectronic assembly comprise: a package substrate having a first face and an opposing second face, the package substrate comprising a conductive trace in a dielectric material, a conductive structure at least partially surrounding the conductive trace and separated from the conductive trace by the dielectric material; and an integrated circuit (IC) die attached to the first face of the package substrate and coupled to the conductive trace by a conductive pathway through the package substrate. The conductive trace has a non-rectangular cross-section with rounded corners, the conductive structure comprises a plurality of conductive planes parallel to the conductive trace and coupled to a ground connection.

公开(公告)号：US11380609B2

公开(公告)日：2022-07-05

申请号：US15985348

申请日：2018-05-21

Applicant: Intel Corporation

Inventor： Cheng Xu ,  Jiwei Sun ,  Ji Yong Park ,  Kyu Oh Lee ,  Yikang Deng ,  Zhichao Zhang ,  Liwei Cheng ,  Andrew James Brown

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a core substrate with a first conductive structure having a first thickness on the core substrate, and a second conductive structure having a second thickness on the core substrate, where the first thickness is different than the second thickness.

公开(公告)号：US11212932B2

公开(公告)日：2021-12-28

申请号：US16888069

申请日：2020-05-29

Applicant: Intel Corporation

Inventor： Srikant Nekkanty ,  Zhichao Zhang ,  Kemal Aygun

IPC: H01R12/00 ,  H05K7/10 ,  H05K1/11 ,  H05K7/14 ,  H05K1/02

Abstract: An interposer and method of providing spatial and arrangement transformation are described. An electronic system has an electronic package, a motherboard and an interposer between the package and the motherboard. The interposer has signal and ground contacts on opposing surfaces that are respectively connected. The contacts opposing the package has a higher signal to ground contact ratio than the contacts opposing the motherboard, as well as different arrangements. Ground shielding vias in the interposer, which are connected to a ground plane, electrically isolate the signals through the interposer. The package may be mounted on a shielded socket such that signal and ground pins are mounted respectively in signal and ground socket mountings, ground shielding vias are between the signal socket mountings, and the ground socket mountings contain plated socket housings.

公开(公告)号：US20210344116A1

公开(公告)日：2021-11-04

申请号：US17373926

申请日：2021-07-13

Applicant: Intel Corporation

Inventor： Sidharth Dalmia ,  Trang Thai ,  William James Lambert ,  Zhichao Zhang ,  Jiwei Sun

IPC: H01Q9/04 ,  H01Q1/22 ,  H01Q1/08

Abstract: Disclosed herein are antenna boards, antenna modules, and communication devices. For example, in some embodiments, an antenna module may include: an antenna patch support including a flexible portion; an integrated circuit (IC) package coupled to the antenna patch support; and an antenna patch coupled to the antenna patch support.

公开(公告)号：US11107757B2

公开(公告)日：2021-08-31

申请号：US16855629

申请日：2020-04-22

Applicant: Intel Corporation

Inventor： Sanka Ganesan ,  William James Lambert ,  Zhichao Zhang ,  Sri Chaitra Jyotsna Chavali ,  Stephen Andrew Smith ,  Michael James Hill ,  Zhenguo Jiang

IPC: H01L21/48 ,  H01L23/498 ,  H01L23/31 ,  H05K1/18 ,  H01L23/00 ,  H01L25/10 ,  H01L25/065 ,  H05K7/02 ,  H01L21/56

Abstract: Disclosed herein are integrated circuit (IC) structures that may be included in package substrates. For example, disclosed herein are passive components in package substrate, wherein the passive components include at least one non-circular via and at least one pad in contact with the at least one non-circular via, and the passive components include an inductor or a capacitor. Other embodiments are also disclosed.

公开(公告)号：US20200296852A1

公开(公告)日：2020-09-17

申请号：US16888069

申请日：2020-05-29

Applicant: Intel Corporation

Inventor： Srikant Nekkanty ,  Zhichao Zhang ,  Kemal Aygun

IPC: H05K7/10 ,  H05K1/11 ,  H05K7/14 ,  H05K1/02

Abstract: An interposer and method of providing spatial and arrangement transformation are described. An electronic system has an electronic package, a motherboard and an interposer between the package and the motherboard. The interposer has signal and ground contacts on opposing surfaces that are respectively connected. The contacts opposing the package has a higher signal to ground contact ratio than the contacts opposing the motherboard, as well as different arrangements. Ground shielding vias in the interposer, which are connected to a ground plane, electrically isolate the signals through the interposer. The package may be mounted on a shielded socket such that signal and ground pins are mounted respectively in signal and ground socket mountings, ground shielding vias are between the signal socket mountings, and the ground socket mountings contain plated socket housings.

公开(公告)号：US10716231B2

公开(公告)日：2020-07-14

申请号：US16146908

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Srikant Nekkanty ,  Zhichao Zhang ,  Kemal Aygun

IPC: H01R12/00 ,  H05K7/10 ,  H05K1/11 ,  H05K7/14 ,  H05K1/02

Abstract: An interposer and method of providing spatial and arrangement transformation are described. An electronic system has an electronic package, a motherboard and an interposer between the package and the motherboard. The interposer has signal and ground contacts on opposing surfaces that are respectively connected. The contacts opposing the package has a higher signal to ground contact ratio than the contacts opposing the motherboard, as well as different arrangements. Ground shielding vias in the interposer, which are connected to a ground plane, electrically isolate the signals through the interposer. The package may be mounted on a shielded socket such that signal and ground pins are mounted respectively in signal and ground socket mountings, ground shielding vias are between the signal socket mountings, and the ground socket mountings contain plated socket housings.

公开(公告)号：US10658765B2

公开(公告)日：2020-05-19

申请号：US16021474

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Sri Chaitra Jyotsna Chavali ,  Sanka Ganesan ,  William J. Lambert ,  Debendra Mallik ,  Zhichao Zhang

IPC: H01Q1/38 ,  H01Q25/00 ,  H01Q9/04

Abstract: A method of forming a planar antenna on a first substrate. An antenna feedline is formed on a peelable copper film of a carrier. A dielectric with no internal conductive layer is formed on the feedline. A planar antenna is formed on one of two parallel sides of the dielectric and a feed port is formed adjacent the other parallel side. The feedline connects the antenna with the feed port. One plane of the planar antenna is configured for perpendicular attachment to a second substrate. The feedline is connected to the planar antenna by a via through the dielectric. The peelable copper is removed and the structure is etched to produce the planar antenna on the substrate. Two planar antennas on substrates can be perpendicularly attached to another substrate to form side-firing antennas.

公开(公告)号：US20190098764A1

公开(公告)日：2019-03-28

申请号：US16081487

申请日：2016-04-02

Applicant: INTEL CORPORATION

Inventor： ERIC LI ,  Kemal Aygun ,  Kai Xiao ,  Gong Ouyang ,  Zhichao Zhang

IPC: H05K3/00 ,  H05K1/02 ,  H05K3/02

Abstract: Fine feature formation techniques for printed circuit boards are described. In one embodiment, for example, a method may comprise fabricating a conductive structure 306 on a low density interconnect (LDI) printed circuit board (PCB) 150 according to an LDI fabrication process and forming one or more fme conductive features on the LDI PCB by performing a fme feature formation (FFF) process, the FFF process to comprise removing conductive material of the conductive structure along an excision path to form a fme gap region 308 within the conductive structure. Other embodiments are described and claimed.