公开(公告)号：US20240429117A1

公开(公告)日：2024-12-26

申请号：US18338176

申请日：2023-06-20

Applicant: Intel Corporation

Inventor： Harshit DHAKAD ,  Georgios C. DOGIAMIS ,  Georg SEIDEMANN ,  Bernd WAIDHAS ,  Thomas WAGNER ,  Manisha DUTTA ,  Michael LANGENBUCH

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/42 ,  H01L23/498 ,  H01L23/552

Abstract: Embodiments herein relate to systems, apparatuses, techniques or processes for reducing the capacitance of a package that includes a die by at least partially surrounding the die within a mold compound and a dielectric material with different dielectric constants. Other embodiments may be described and/or claimed.