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    GROOVED PACKAGE
    3.
    发明公开
    GROOVED PACKAGE 审中-公开

    公开(公告)号：US20230317536A1

    公开(公告)日：2023-10-05

    申请号：US17707536

    申请日：2022-03-29

    Applicant: Intel Corporation

    Inventor： Georg SEIDEMANN ,  Bernd WAIDHAS ,  Thomas WAGNER ,  Stephan STOECKL

    IPC: H01L23/31 ,  H01L23/538 ,  H01L25/065 ,  H01L21/56

    CPC classification number: H01L23/3107 ,  H01L23/5381 ,  H01L25/0655 ,  H01L21/56

    Abstract: Embodiments herein relate to systems, apparatuses, techniques or processes related to packages that are fully or partially encapsulated in a mold material, with one or more grooves in the mold material to reduce failure in the package during operation. In embodiments, the grooves will allow greater flexibility within the body of the package as it experiences thermo-mechanical stress during operation and will reduce stresses that may be placed on internal components such as chips or bridges in the package, as well as stresses that may be placed on interconnects of the package that are coupled to a substrate. Other embodiments may be described and/or claimed.

    STRESS RELIEF DIE IMPLEMENTATION
    5.
    发明申请
    STRESS RELIEF DIE IMPLEMENTATION 有权

    公开(公告)号：US20210193594A1

    公开(公告)日：2021-06-24

    申请号：US16721095

    申请日：2019-12-19

    Applicant: Intel Corporation

    Inventor： Stephan STOECKL ,  Wolfgang MOLZER ,  Georg SEIDEMANN ,  Bernd WAIDHAS

    IPC: H01L23/58 ,  H01L23/31 ,  H01L49/02 ,  H01L21/683 ,  H01L21/56

    Abstract: Embodiments disclosed herein include semiconductor packages. In a particular embodiment, the semiconductor package is a wafer level chip scale package (WLCSP). In an embodiment, the WLCSP comprises a die. In an embodiment, the die comprises an active surface and a backside surface. The die has a first coefficient of thermal expansion (CTE). In an embodiment, the WLCSP further comprises a channel into the die. In an embodiment, the channel is filled with a stress relief material, where the stress relief material has a second CTE that is greater than the first CTE.

    METHOD TO IMPLEMENT WAFER-LEVEL CHIP-SCALE PACKAGES WITH GROUNDED CONFORMAL SHIELD
    6.
    发明申请
    METHOD TO IMPLEMENT WAFER-LEVEL CHIP-SCALE PACKAGES WITH GROUNDED CONFORMAL SHIELD 审中-公开

    公开(公告)号：US20200312781A1

    公开(公告)日：2020-10-01

    申请号：US16368032

    申请日：2019-03-28

    Applicant: Intel Corporation

    Inventor： Gianni SIGNORINI ,  Georg SEIDEMANN ,  Bernd WAIDHAS

    IPC: H01L23/552 ,  H01L23/498 ,  H01L23/31 ,  H01L21/48 ,  H01L21/78

    Abstract: Embodiments disclosed herein include electronic packages with conformal shields and methods of forming such packages. In an embodiment, the electronic package comprises a die having a first surface, a second surface opposite the first surface, and sidewall surfaces. A redistribution layer is over the first surface of the die, and the redistribution layer comprises a first conductive layer. In an embodiment, an under ball metallization (UBM) layer is over the redistribution layer, and a conductive shield is over the sidewall surfaces of the die and the second surface of the die. In an embodiment, the conductive shield is electrically coupled to the UBM layer.

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