公开(公告)号：US20240429117A1

公开(公告)日：2024-12-26

申请号：US18338176

申请日：2023-06-20

Applicant: Intel Corporation

Inventor： Harshit DHAKAD ,  Georgios C. DOGIAMIS ,  Georg SEIDEMANN ,  Bernd WAIDHAS ,  Thomas WAGNER ,  Manisha DUTTA ,  Michael LANGENBUCH

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/42 ,  H01L23/498 ,  H01L23/552

Abstract: Embodiments herein relate to systems, apparatuses, techniques or processes for reducing the capacitance of a package that includes a die by at least partially surrounding the die within a mold compound and a dielectric material with different dielectric constants. Other embodiments may be described and/or claimed.

公开(公告)号：US20240364023A1

公开(公告)日：2024-10-31

申请号：US18140346

申请日：2023-04-27

Applicant: Intel Corporation

Inventor： Thomas WAGNER ,  Georg SEIDEMANN ,  Tae Young YANG ,  Harald GOSSNER ,  Telesphor KAMGAING ,  Bernd WAIDHAS

IPC: H01Q21/20 ,  H01Q5/35

CPC classification number: H01Q21/205 ,  H01Q5/35

Abstract: Embodiments disclosed herein include a communication module. In an embodiment, the communication module comprises a package substrate, and a die on the package substrate. In an embodiment, a plurality of antennas are around the die. In an embodiment, the plurality of antennas are coupled to the die by a plurality of traces, and heights of each of the plurality of antennas is greater than a thickness of the traces.

公开(公告)号：US20240030175A1

公开(公告)日：2024-01-25

申请号：US18374582

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Gianni SIGNORINI ,  Veronica SCIRIHA ,  Thomas WAGNER

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L24/20 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L2221/68372 ,  H01L2224/214 ,  H01L2924/15311 ,  H01L2924/19104

Abstract: In accordance with disclosed embodiments, there is a method of integrating and accessing passive components in three-dimensional fan-out wafer-level packages. One example is a microelectronic die package that includes a die, a package substrate attached to the die on one side of the die and configured to be connected to a system board, a plurality of passive devices over a second side of the die, and a plurality of passive device contacts over a respective passive die, the contacts being configured to be coupled to a second die mounted over the passive devices and over the second side of the die.

公开(公告)号：US20220238440A1

公开(公告)日：2022-07-28

申请号：US17716958

申请日：2022-04-08

Applicant: Intel Corporation

Inventor： Georg SEIDEMANN ,  Thomas WAGNER ,  Adreas WOLTER ,  Bernd WAIDHAS

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/48 ,  H01L23/532 ,  H01L23/00 ,  H01L23/538 ,  H01L25/16 ,  H01L25/065 ,  H01L21/56

Abstract: A system-in-package apparatus includes a semiconductive bridge that uses bare-die pillars to couple with a semiconductive device such as a processor die. The apparatus achieves a thin form factor.

公开(公告)号：US20210305158A1

公开(公告)日：2021-09-30

申请号：US16833169

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Thomas WAGNER ,  Jan PROSCHWITZ

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/00 ,  H01L23/552

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a redistribution layer (RDL) having a conductive layer in a first dielectric layer, and a second dielectric layer over the conductive and first dielectric layers. The RDL comprises an extended portion having a first thickness that vertically extends from a bottom surface of the first dielectric layer to a topmost surface of the second dielectric layer. The electronic package comprises a die on the RDL, where the die has sidewall surfaces, a top surface, and a bottom surface that is opposite from the top surface, and an active region on the bottom surface of the die. The first thickness is greater than a second thickness of the RDL that vertically extends from the bottom surface of the first dielectric layer to the bottom surface of the die. The extended portion is over and around the sidewall surfaces.

公开(公告)号：US20200006293A1

公开(公告)日：2020-01-02

申请号：US16024700

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Robert SANKMAN ,  Sanka GANESAN ,  Bernd WAIDHAS ,  Thomas WAGNER ,  Lizabeth KESER

IPC: H01L25/065

Abstract: Embodiments disclosed herein include an electronics package comprising stacked dies. In an embodiment, the electronics package comprises a first die that includes a plurality of first conductive interconnects extending out from a first surface of the first die. In an embodiment, the first die further comprises a keep out zone. In an embodiment, the electronic package may also comprise a second die. In an embodiment, the second die is positioned entirely within a perimeter of the keep out zone of the first die. In an embodiment, a first surface of the second die faces the first surface of the first die.

公开(公告)号：US20250112139A1

公开(公告)日：2025-04-03

申请号：US18374954

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Abdallah BACHA ,  Thomas WAGNER ,  Cindy MUIR ,  Mohan Prashanth JAVARE GOWDA ,  Stephan STOECKL ,  Wolfgang MOLZER

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/31 ,  H01L23/48 ,  H01L23/538 ,  H01L25/065

Abstract: Embodiments herein relate to systems, apparatuses, or processes for forming a die that has active circuitry within the die and also one or more vias that extend through the die that are electrically isolated from the active circuitry. In embodiments, the active circuitry may be within a region within a die, for example in the center of the die, and the vias may be in an extended area around the active circuitry of the die. In embodiments, an existing die may be provided, and an extended area may be formed on the existing die into which the vias may be placed. Other embodiments may be described and/or claimed.

公开(公告)号：US20240128223A1

公开(公告)日：2024-04-18

申请号：US18399220

申请日：2023-12-28

Applicant: Intel Corporation

Inventor： Bernd WAIDHAS ,  Andreas WOLTER ,  Georg SEIDEMANN ,  Thomas WAGNER

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L24/20 ,  H01L23/3157 ,  H01L23/5386 ,  H01L24/06 ,  H01L24/13 ,  H01L2924/3511 ,  H01L2924/381

Abstract: Embodiments disclosed herein include electronic package and methods of forming such packages. In an embodiment, an electronic package comprises a mold layer and a first die embedded in the mold layer. In an embodiment, the first die comprises first pads at a first pitch and second pads at a second pitch. In an embodiment, the electronic package further comprises a second die embedded in the mold layer, where the second die comprises third pads at the first pitch and fourth pads at the second pitch. In an embodiment, a bridge die is embedded in the mold layer, and the bridge die electrically couples the second pads to the fourth pads.

公开(公告)号：US20230317536A1

公开(公告)日：2023-10-05

申请号：US17707536

申请日：2022-03-29

Applicant: Intel Corporation

Inventor： Georg SEIDEMANN ,  Bernd WAIDHAS ,  Thomas WAGNER ,  Stephan STOECKL

IPC: H01L23/31 ,  H01L23/538 ,  H01L25/065 ,  H01L21/56

CPC classification number: H01L23/3107 ,  H01L23/5381 ,  H01L25/0655 ,  H01L21/56

Abstract: Embodiments herein relate to systems, apparatuses, techniques or processes related to packages that are fully or partially encapsulated in a mold material, with one or more grooves in the mold material to reduce failure in the package during operation. In embodiments, the grooves will allow greater flexibility within the body of the package as it experiences thermo-mechanical stress during operation and will reduce stresses that may be placed on internal components such as chips or bridges in the package, as well as stresses that may be placed on interconnects of the package that are coupled to a substrate. Other embodiments may be described and/or claimed.

公开(公告)号：US20230197537A1

公开(公告)日：2023-06-22

申请号：US17644801

申请日：2021-12-17

Applicant: Intel Corporation

Inventor： Richard GEIGER ,  Klaus HEROLD ,  Harald GOSSNER ,  Martin OSTERMAYR ,  Georgios PANAGOPOULOS ,  Johannes RAUH ,  Joachim SINGER ,  Thomas WAGNER

IPC: H01L21/66 ,  H01L23/48

CPC classification number: H01L22/32 ,  H01L23/481

Abstract: A semiconductor structure is provided. The semiconductor structure includes a plurality of transistors arranged at a front side of a semiconductor substrate and a test structure located at the front side of the semiconductor substrate. Further, the semiconductor structure comprises a first electrically conductive connection extending from the test structure through the semiconductor substrate to a backside test pad arranged at a backside of the semiconductor substrate.