公开(公告)号：US20240241854A1

公开(公告)日：2024-07-18

申请号：US18619217

申请日：2024-03-28

Applicant: Intel Corporation

Inventor： Garrett CLAY ,  Jaemon FRANKO ,  Heung-for CHENG

IPC: G06F15/80 ,  G06F1/20

CPC classification number: G06F15/80 ,  G06F1/206

Abstract: Some aspects of the present disclosure relate to an apparatus comprising memory circuitry, machine-readable instructions, and processor circuitry to execute the machine-readable instructions to obtain a physical layout of a first processor circuitry comprising a plurality of processor cores and thermal information of the plurality of processor cores and to determine a first processor core of the plurality of processor cores to execute a first work-load based on the physical layout of the first processor circuitry and the thermal information of the plurality of processor cores.