公开(公告)号：US20210194473A1

公开(公告)日：2021-06-24

申请号：US16724564

申请日：2019-12-23

Applicant: Intel Corporation

Inventor： Hundo SHIN ,  Kameran AZADET ,  Martin CLARA ,  Daniel GRUBER

IPC: H03K5/13

Abstract: An apparatus for generating a plurality of phase-shifted clock signals is provided. The apparatus comprises a first input node configured to receive a first reference clock signal. Further, the apparatus comprises a second input node configured to receive a second reference clock signal. The apparatus comprises a plurality of output nodes each configured to output one of the plurality of phase-shifted clock signals. Additionally, the apparatus comprises a cascade of coupled clock generation circuits configured to generate the plurality of phase-shifted clock signals based on the first reference clock signal and the second reference clock signal. Input nodes of the first clock generation circuit of the cascade of clock generation circuits are coupled to the first input node and the second input node. Output nodes of the last clock generation circuit of the cascade of clock generation circuits are coupled to the plurality of output nodes. At least one of the plurality of clock generation circuits is an active circuit, and at least one of the plurality of clock generation circuits is a passive circuit.

公开(公告)号：US20220294462A1

公开(公告)日：2022-09-15

申请号：US17754148

申请日：2019-12-23

Applicant: Intel Corporation

Inventor： Daniel GRUBER ,  Kameran AZADET ,  Yu-Shan WANG ,  Hundo SHIN ,  Martin CLARA

IPC: H03M1/06 ,  H04B1/04 ,  H04B1/10

Abstract: A Digital-to-Analog Converter, DAC, is provided. The DAC comprises one or more first DAC cells configured to generate a first analog signal based on first digital data. The one or more first DAC cells are coupled to a first output node for coupling to a first load. The DAC comprises one or more second DAC cells configured to generate a second analog signal based on second digital data. The one or more second DAC cells are coupled to a second output node for coupling to a second load. The one or more first DAC cells and the one or more second DAC cells are couplable to a power supply for drawing a supply current. The DAC further comprises a data generation circuit configured to generate the second digital data based on the first digital data.

公开(公告)号：US20210191455A1

公开(公告)日：2021-06-24

申请号：US16724486

申请日：2019-12-23

Applicant: Intel Corporation

Inventor： Yu-Shan WANG ,  Martin CLARA ,  Daniel GRUBER ,  Hundo SHIN ,  Kameran AZADET

IPC: G06F1/12 ,  G06F1/08 ,  G06F1/14

Abstract: An apparatus for generating synchronized clock signals is provided. The apparatus comprises a first circuit comprising a clock divider circuit configured to receive a first clock signal and to generate a second clock signal by frequency dividing the first clock signal. Further, the apparatus comprises a one or more second circuits comprising a respective synchronization circuit configured to receive the first clock signal. The synchronization circuit of one of the one or more second circuits is configured to receive the second clock signal from the first circuit and to resample the second clock signal based on the first clock signal in order to generate a replica of the second clock signal that is in phase with the second clock signal.

公开(公告)号：US20220345148A1

公开(公告)日：2022-10-27

申请号：US17754310

申请日：2019-12-23

Applicant: Intel Corporation

Inventor： Albert MOLINA ,  Kameran AZADET ,  Martin CLARA ,  Hundo SHIN

IPC: H03M1/80

Abstract: A digital-to-analog converter is provided. The digital-to-analog converter comprises a delay circuit configured to iteratively delay a digital input signal based on a clock signal for generating a plurality of delayed digital input signals. Further, the digital-to-analog converter comprises a plurality of groups of inverter cells. Each group of inverter cells is configured to generate a respective analog signal based on one of the plurality of delayed digital input signals. The inverter cells comprise a respective inverter circuit configured to invert the respective delayed digital input signal. The plurality of groups of inverter cells comprise different numbers of inverter cells. The digital-to-analog converter additionally comprises an output configured to output an analog output signal based on the analog signals of the plurality of groups of inverter cells.

公开(公告)号：US20220345144A1

公开(公告)日：2022-10-27

申请号：US17753917

申请日：2019-12-23

Applicant: Intel Corporation

Inventor： Kameran AZADET ,  Martin CLARA ,  Daniel GRUBER ,  Albert MOLINA ,  Hundo SHIN

IPC: H03M1/10 ,  G01R31/28 ,  G01R31/3187

Abstract: A semiconductor chip providing on-chip self-testing of an Analog-to-Digital Converter, ADC, implemented in the semiconductor chip is provided. The semiconductor chip comprises the ADC and a Digital-to-Analog Converter, DAC, configured to generate and supply a radio frequency test signal to the ADC via a supply path. The ADC is configured to generate digital output data based on the radio frequency test signal. The semiconductor chip further comprises a reference data generation circuit configured to generate digital reference data. Additionally, the semiconductor chip comprises a comparator circuit configured to compare the digital output data to the digital reference in order to determine error data.

公开(公告)号：US20210385119A1

公开(公告)日：2021-12-09

申请号：US17351288

申请日：2021-06-18

Applicant: Intel Corporation

Inventor： Kameran AZADET ,  Martin CLARA ,  Daniel GRUBER ,  Christian LINDHOLM ,  Hundo SHIN

IPC: H04L27/36 ,  H03M1/06 ,  H03M1/10

Abstract: An Analog-to-Digital Converter, ADC, system is provided. The ADC system comprises a plurality of ADC circuits and a first input for receiving a transmit signal of a transceiver. One ADC circuit of the plurality of ADC circuits is coupled to the first input and configured to provide first digital data based on the transmit signal. The ADC system further comprises a second input for receiving a receive signal of the transceiver. The other ADC circuits of the plurality of ADC circuits are coupled to the second input, wherein the other ADC circuits of the plurality of ADC circuits are time-interleaved and configured to provide second digital data based on the receive signal. Additionally, the ADC system comprises a first output configured to output digital feedback data based on the first digital data, and a second output configured to output digital receive data based on the second digital data.

公开(公告)号：US20200313684A1

公开(公告)日：2020-10-01

申请号：US16369276

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Daniel GRUBER ,  Franz KUTTNER ,  Davide PONTON ,  Kameran AZADET ,  Hundo SHIN ,  Martin CLARA ,  Matej KUS

IPC: H03M1/06 ,  H04B1/04

Abstract: A digital-to-analog converter is provided. The digital-to-analog converter includes a plurality of digital-to-analog converter cells coupled to an output node of the digital-to-analog converter. At least one of the plurality of digital-to-analog converter cells includes a capacitive element configured to generate an analog cell output signal based on a drive signal. The at least one of the plurality of digital-to-analog converter cells further includes a driver circuit configured to generate the drive signal, and a resistive element exhibiting a resistance of at least 20Ω. The resistive element is coupled between the driver circuit and the capacitive element or between the capacitive element and the output node.