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公开(公告)号：US20240007083A1
公开(公告)日：2024-01-04
申请号：US17809906
申请日：2022-06-30
Applicant: Intel Corporation
Inventor： Martin CLARA , Giacomo CASCIO , Erfan GHADERI , Marc Jan Georges TIEBOUT
CPC classification number: H03H11/245 , H04B1/40
Abstract: A digital step attenuator for automatic gain control in a transceiver front-end. The digital step attenuator includes a series path coupled between an input port and an output port, a plurality of series shunt switches coupled in parallel to the series path, and a plurality of parallel paths coupled to the series path in parallel. The series path includes a plurality of series resistors coupled in series. Each series shunt switch is for by-passing a different set of one or more series resistors. Each parallel path includes a parallel resistor and a parallel shunt switch, and each parallel path is coupled to either the input port, the output port, or an internal node between two adjacent series resistors, in parallel. A plurality of different π-attenuators with a different topology are formed by selectively controlling the series shunt switches and the parallel shunt switches.
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公开(公告)号：US20230208429A1
公开(公告)日：2023-06-29
申请号：US17645785
申请日：2021-12-23
Applicant: Intel Corporation
Inventor： Albert MOLINA , Kameran AZADET , Martin CLARA , Daniel GRUBER
IPC: H03M1/10
CPC classification number: H03M1/1014
Abstract: A system and method for calibrating a time-interleaved digital-to-analog converter (DAC). A calibration signal generator generates calibration data, and a time-interleaved DAC converts the calibration data to an analog calibration signal. An observation analog-to-digital converter (ADC) samples, and quantizes, the analog calibration signal filtered by an anti-alias filter. A mismatch estimation block estimates a frequency response mismatch between the sub-DACs and generates a sub-DAC mismatch correction factor based on an output of the observation ADC. The calibration signal generator applies the sub-DAC mismatch correction factor to the calibration data. The mismatch estimation block may estimate a DC offset mismatch between the sub-DACs based on the output of the observation ADC and generates a DC offset correction factor, and the calibration signal generator applies the DC offset correction factor to the calibration data.
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公开(公告)号：US20220294462A1
公开(公告)日：2022-09-15
申请号：US17754148
申请日：2019-12-23
Applicant: Intel Corporation
Inventor： Daniel GRUBER , Kameran AZADET , Yu-Shan WANG , Hundo SHIN , Martin CLARA
Abstract: A Digital-to-Analog Converter, DAC, is provided. The DAC comprises one or more first DAC cells configured to generate a first analog signal based on first digital data. The one or more first DAC cells are coupled to a first output node for coupling to a first load. The DAC comprises one or more second DAC cells configured to generate a second analog signal based on second digital data. The one or more second DAC cells are coupled to a second output node for coupling to a second load. The one or more first DAC cells and the one or more second DAC cells are couplable to a power supply for drawing a supply current. The DAC further comprises a data generation circuit configured to generate the second digital data based on the first digital data.
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公开(公告)号：US20220200615A1
公开(公告)日：2022-06-23
申请号：US17131811
申请日：2020-12-23
Applicant: Intel Corporation
Inventor： Daniel GRUBER , Christian LINDHOLM , Martin CLARA , Giacomo CASCIO
IPC: H03M1/08 , H03K19/003 , H03K19/0185 , H04B1/12
Abstract: A reference buffer circuit for an analog-to-digital converter is provided. The reference buffer circuit includes a first input node configured to receive a first bias signal of a first polarity from a first signal line. Further, the reference buffer circuit includes a second input node configured to receive a second bias signal of a second polarity from a second signal line. Additionally, the reference buffer circuit includes a first output node configured to output a first reference signal of the first polarity. A first buffer amplifier is coupled between the first input node and the first output node. The reference buffer circuit includes in addition a second output node configured to output a second reference signal of the second polarity. A second buffer amplifier is coupled between the second input node and the second output node. Further, the reference buffer circuit includes a first coupling path comprising a first capacitive element. The first coupling path is coupled between the first output node and the second input node. In addition, the reference buffer circuit includes a second coupling path comprising a second capacitive element. The second coupling path is coupled between the second output node and the first input node.
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公开(公告)号：US20220200613A1
公开(公告)日：2022-06-23
申请号：US17131868
申请日：2020-12-23
Applicant: Intel Corporation
Inventor： Daniel GRUBER , Matteo CAMPONESCHI , Christian LINDHOLM , Martin CLARA , Giacomo CASCIO
Abstract: An input buffer circuit for an analog-to-digital converter is provided. The input buffer circuit includes a buffer amplifier. The buffer amplifier includes a first input node and a second input node each configured to receive a respective one of a first input signal and a second input signal forming a differential input signal pair for the analog-to-digital converter. The buffer amplifier further includes a first output node and a second output node each configured to output a respective one of a first buffered signal and a second buffered signal. In addition, the input buffer circuit includes feedback circuitry. The feedback circuitry is configured to generate, based on the first buffered signal and the second buffered signal, a first feedback signal and a second feedback signal for mitigating a respective unwanted signal component at the first input node and the second input node related to a limited reverse isolation of the amplifier buffer. The feedback circuitry is further configured to supply the first feedback signal to the first input node and the second feedback signal to the second input node.
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Patent Agency Ranking
公开(公告)号：US20210191455A1
公开(公告)日：2021-06-24
申请号：US16724486
申请日：2019-12-23
Applicant: Intel Corporation
Inventor： Yu-Shan WANG , Martin CLARA , Daniel GRUBER , Hundo SHIN , Kameran AZADET
Abstract: An apparatus for generating synchronized clock signals is provided. The apparatus comprises a first circuit comprising a clock divider circuit configured to receive a first clock signal and to generate a second clock signal by frequency dividing the first clock signal. Further, the apparatus comprises a one or more second circuits comprising a respective synchronization circuit configured to receive the first clock signal. The synchronization circuit of one of the one or more second circuits is configured to receive the second clock signal from the first circuit and to resample the second clock signal based on the first clock signal in order to generate a replica of the second clock signal that is in phase with the second clock signal.
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公开(公告)号：US20230198536A1
公开(公告)日：2023-06-22
申请号：US17645461
申请日：2021-12-22
Applicant: Intel Corporation
Inventor： Albert MOLINA , Kameran AZADET , Martin CLARA
CPC classification number: H03M1/1033 , H03M1/0629
Abstract: An analog-to-digital conversion system. A clock generator generates a first clock signal at a first frequency. An analog-to-digital converter (ADC) converts an input analog signal to a digital signal. The ADC operates based on the first clock signal at the first frequency. A calibration digital-to-analog converter (DAC) generates an analog reference signal from digital reference data. A fractional rate clock generator generates a second clock signal from the first clock signal. The second clock signal is at a second frequency that is a fractional rate of the first frequency, and the calibration DAC operates at the second frequency. An equalizer processes an output of the ADC to remove a distortion incurred by the ADC and a calibration circuitry generates coefficients for the equalizer based on the digital reference data and the output of the ADC to the analog reference signal.
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公开(公告)号：US20220345146A1
公开(公告)日：2022-10-27
申请号：US17754309
申请日：2019-12-27
Applicant: Intel Corporation
Inventor： Albert MOLINA , Kameran AZADET , Martin CLARA , Matteo CAMPONESCHI , Christian LINDHOLM
IPC: H03M1/46
Abstract: An analog-to-digital converter comprising a plurality of sampling cells. At least one of the plurality of sampling cells comprises a capacitive element coupled to a cell output of the at least one of the plurality of sampling cells, wherein a cell output signal is provided at the cell output. The at least one of the plurality of sampling cells further comprises a first cell input for receiving an input signal to be digitized, and a second cell input for receiving a calibration signal. Additionally, the at least one of the plurality of sampling cells comprises a first switch circuit capable of selectively coupling the first cell input to the capacitive element based on a clock signal, and a second switch circuit capable of selectively coupling the second cell input to the capacitive element, wherein a size of the second switch circuit is smaller than a size of the first switch circuit.
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公开(公告)号：US20210194473A1
公开(公告)日：2021-06-24
申请号：US16724564
申请日：2019-12-23
Applicant: Intel Corporation
Inventor： Hundo SHIN , Kameran AZADET , Martin CLARA , Daniel GRUBER
IPC: H03K5/13
Abstract: An apparatus for generating a plurality of phase-shifted clock signals is provided. The apparatus comprises a first input node configured to receive a first reference clock signal. Further, the apparatus comprises a second input node configured to receive a second reference clock signal. The apparatus comprises a plurality of output nodes each configured to output one of the plurality of phase-shifted clock signals. Additionally, the apparatus comprises a cascade of coupled clock generation circuits configured to generate the plurality of phase-shifted clock signals based on the first reference clock signal and the second reference clock signal. Input nodes of the first clock generation circuit of the cascade of clock generation circuits are coupled to the first input node and the second input node. Output nodes of the last clock generation circuit of the cascade of clock generation circuits are coupled to the plurality of output nodes. At least one of the plurality of clock generation circuits is an active circuit, and at least one of the plurality of clock generation circuits is a passive circuit.
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公开(公告)号：US20210050870A1
公开(公告)日：2021-02-18
申请号：US16924274
申请日：2020-07-09
Applicant: Intel Corporation
Inventor： Daniel GRUBER , Ramon SANCHEZ , Kameran AZADET , Martin CLARA
Abstract: A digital-to-analog conversion system is provided. The digital-to-analog conversion system includes a digital-to-analog converter configured to receive a pre-distorted digital signal from a digital circuit, and to generate an analog signal based on the pre-distorted digital signal. Further, the digital-to-analog conversion system includes a feedback loop for providing a digital feedback signal to the digital circuit. The feedback loop includes an analog-to-digital converter configured to generate the digital feedback signal based on the analog signal, and wherein a sample rate of the analog-to-digital converter is lower than a sample rate of the digital-to-analog converter.
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