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    System and method for calibrating a time-interleaved digital-to-analog converter
    2.
    发明公开
    System and method for calibrating a time-interleaved digital-to-analog converter 审中-公开

    公开(公告)号：US20230208429A1

    公开(公告)日：2023-06-29

    申请号：US17645785

    申请日：2021-12-23

    Applicant: Intel Corporation

    Inventor： Albert MOLINA ,  Kameran AZADET ,  Martin CLARA ,  Daniel GRUBER

    IPC: H03M1/10

    CPC classification number: H03M1/1014

    Abstract: A system and method for calibrating a time-interleaved digital-to-analog converter (DAC). A calibration signal generator generates calibration data, and a time-interleaved DAC converts the calibration data to an analog calibration signal. An observation analog-to-digital converter (ADC) samples, and quantizes, the analog calibration signal filtered by an anti-alias filter. A mismatch estimation block estimates a frequency response mismatch between the sub-DACs and generates a sub-DAC mismatch correction factor based on an output of the observation ADC. The calibration signal generator applies the sub-DAC mismatch correction factor to the calibration data. The mismatch estimation block may estimate a DC offset mismatch between the sub-DACs based on the output of the observation ADC and generates a DC offset correction factor, and the calibration signal generator applies the DC offset correction factor to the calibration data.

    DIGITAL-TO-ANALOG CONVERTER, DATA PROCESSING SYSTEM, BASE STATION, AND MOBILE DEVICE
    3.
    发明申请
    DIGITAL-TO-ANALOG CONVERTER, DATA PROCESSING SYSTEM, BASE STATION, AND MOBILE DEVICE 有权

    公开(公告)号：US20220294462A1

    公开(公告)日：2022-09-15

    申请号：US17754148

    申请日：2019-12-23

    Applicant: Intel Corporation

    Inventor： Daniel GRUBER ,  Kameran AZADET ,  Yu-Shan WANG ,  Hundo SHIN ,  Martin CLARA

    IPC: H03M1/06 ,  H04B1/04 ,  H04B1/10

    Abstract: A Digital-to-Analog Converter, DAC, is provided. The DAC comprises one or more first DAC cells configured to generate a first analog signal based on first digital data. The one or more first DAC cells are coupled to a first output node for coupling to a first load. The DAC comprises one or more second DAC cells configured to generate a second analog signal based on second digital data. The one or more second DAC cells are coupled to a second output node for coupling to a second load. The one or more first DAC cells and the one or more second DAC cells are couplable to a power supply for drawing a supply current. The DAC further comprises a data generation circuit configured to generate the second digital data based on the first digital data.

    APPARATUS FOR GENERATING SYNCHRONIZED CLOCK SIGNALS, ELEC-TRONIC SYSTEM, BASE STATION AND MOBILE DEVICE
    4.
    发明申请
    APPARATUS FOR GENERATING SYNCHRONIZED CLOCK SIGNALS, ELEC-TRONIC SYSTEM, BASE STATION AND MOBILE DEVICE 有权

    公开(公告)号：US20210191455A1

    公开(公告)日：2021-06-24

    申请号：US16724486

    申请日：2019-12-23

    Applicant: Intel Corporation

    Inventor： Yu-Shan WANG ,  Martin CLARA ,  Daniel GRUBER ,  Hundo SHIN ,  Kameran AZADET

    IPC: G06F1/12 ,  G06F1/08 ,  G06F1/14

    Abstract: An apparatus for generating synchronized clock signals is provided. The apparatus comprises a first circuit comprising a clock divider circuit configured to receive a first clock signal and to generate a second clock signal by frequency dividing the first clock signal. Further, the apparatus comprises a one or more second circuits comprising a respective synchronization circuit configured to receive the first clock signal. The synchronization circuit of one of the one or more second circuits is configured to receive the second clock signal from the first circuit and to resample the second clock signal based on the first clock signal in order to generate a replica of the second clock signal that is in phase with the second clock signal.

    Method and apparatus for crest factor reduction
    6.
    发明公开
    Method and apparatus for crest factor reduction 审中-公开

    公开(公告)号：US20240223228A1

    公开(公告)日：2024-07-04

    申请号：US18147720

    申请日：2022-12-29

    Applicant: Intel Corporation

    Inventor： Kannan RAJAMANI ,  Sunitha MOTIPALLI ,  Albert MOLINA ,  Joseph OTHMER ,  Kameran AZADET

    IPC: H04B1/04 ,  H04L27/26

    CPC classification number: H04B1/0475 ,  H04L27/2623 ,  H04B2001/0408 ,  H04B2201/70706

    Abstract: An apparatus and method for performing crest factor reduction (CFR). A peak detection circuit detects peaks from input signal samples based on a first threshold. The first threshold is higher than a second threshold that is determined based on a target peak-to-average power ratio (PAPR). A gain computation circuit determines a gain factor for at least one detected peak. A scaled cancellation pulse generation circuit generates a scaled cancellation pulse for the at least one detected peak based on the gain factor. A combiner circuit combines the scaled cancellation pulse with the input signal samples to generate an output signal. A hard clipping circuit may compress the output signal based on the second threshold. The first threshold is set slightly higher than the second threshold.

    SEMICONDUCTOR DEVICES, TRANSCEIVER, BASE STATION AND MOBILE DEVICE
    7.
    发明公开
    SEMICONDUCTOR DEVICES, TRANSCEIVER, BASE STATION AND MOBILE DEVICE 审中-公开

    公开(公告)号：US20230198542A1

    公开(公告)日：2023-06-22

    申请号：US18054628

    申请日：2022-11-11

    Applicant: Intel Corporation

    Inventor： Daniel GRUBER ,  Kameran AZADET ,  Martin CLARA ,  Marc Jan Georges TIEBOUT

    IPC: H03M1/66 ,  H04B1/04

    CPC classification number: H03M1/66 ,  H04B1/04 ,  H04B2001/045

    Abstract: A semiconductor device comprising at least one transmit path is provided. The transmit path comprises an input node for receiving a digital baseband signal. Further, the transmit path comprises digital mixer circuitry coupled to the input node and configured to generate an upconverted digital baseband signal by upconverting a frequency of the digital baseband signal. Additionally, the transmit path comprises Digital-to-Analog Converter (DAC) circuitry coupled to the digital mixer circuitry and configured to generate an analog radio frequency signal based on the upconverted digital baseband signal. The transmit path comprises first analog mixer circuitry coupleable to an output of the DAC circuitry, and second analog mixer circuitry coupleable to the output of the DAC circuitry. Further, the transmit path comprises a first output node coupleable to an output of the first analog mixer circuitry, and a second output node coupleable to an output of the second analog mixer circuitry.

    METHOD AND SYSTEM FOR DIGITAL EQUALIZATION OF A LINEAR OR NON-LINEAR SYSTEM
    8.
    发明申请
    METHOD AND SYSTEM FOR DIGITAL EQUALIZATION OF A LINEAR OR NON-LINEAR SYSTEM 有权

    公开(公告)号：US20230015514A1

    公开(公告)日：2023-01-19

    申请号：US17358044

    申请日：2021-06-25

    Applicant: Intel Corporation

    Inventor： Albert MOLINA ,  Martin CLARA ,  Kameran AZADET

    IPC: H03M1/10 ,  H03M1/06

    Abstract: A system and method for equalization of a linear or non-linear system. The system includes an adder configured to add an analog reference signal and an input signal, a processing system configured to process a sum of the analog reference signal and the input signal, a non-linear equalizer (NLEQ) configured to process an output of the processing system to remove a distortion incurred by the processing system, a calibration circuitry configured to generate a reconstructed reference signal in digital domain based on measurement of the analog reference signal, and generate coefficients for the NLEQ based on the reconstructed reference signal and the output of the processing system, and a subtractor configured to subtract the reconstructed reference signal from an output of the NLEQ. The analog reference signal may be a sinusoid including single or multiple tones of sinusoids. The non-linear system may be an analog-to-digital converter (ADC).

    APPARATUS FOR CORRECTING A MISMATCH, DIGITAL-TO-ANALOG CONVERTER SYSTEM, TRANSMITTER, BASE STATION, MOBILE DEVICE AND METHOD FOR CORRECTING A MISMATCH
    9.
    发明申请
    APPARATUS FOR CORRECTING A MISMATCH, DIGITAL-TO-ANALOG CONVERTER SYSTEM, TRANSMITTER, BASE STATION, MOBILE DEVICE AND METHOD FOR CORRECTING A MISMATCH 有权

    公开(公告)号：US20220345143A1

    公开(公告)日：2022-10-27

    申请号：US17754308

    申请日：2019-12-27

    Applicant: Intel Corporation

    Inventor： Daniel GRUBER ,  Ramon SANCHEZ ,  Kameran AZADET ,  Martin CLARA

    IPC: H03M1/10 ,  H03M1/06

    Abstract: An apparatus for correcting a mismatch between a first segment and a second segment of a Digital-to-Analog Converter, DAC, is provided. The first segment generates a first contribution to an analog output signal of the DAC based on a first number of bits of a digital input word for the DAC converter, and the second segment generates a second contribution to the analog output signal based on a second number of bits of the digital input word. The apparatus comprises an input configured to receive the digital input word. Further, the apparatus comprises a first processing circuit for the first number of bits comprising a first filter configured to modify the first number of bits in order to generate first modified bits, and a second processing circuit for the second number of bits comprising a second filter configured to modify the second number of bits in order to generate second modified bits. The apparatus additionally comprises an output configured to output a modified digital input word for the DAC. The modified digital input word is based on the first modified bits and the second modified bits.

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