Bridge die design for high bandwidth memory interface

    公开(公告)号:US11094633B2

    公开(公告)日:2021-08-17

    申请号:US16305758

    申请日:2016-06-30

    Abstract: A microelectronic package bridge can comprising a plurality of ground layers, and a plurality of signal layers interwoven with the plurality of ground layers. Each of the signal layers can include a plurality of electrically conductive pathways. Each of the electrically conductive pathways can be arranged to form an electrical connection between one of a first plurality of bumps of a first die and one of a second plurality of bumps of a second die. Each of the plurality of electrically conductive pathways can have a length substantially equal to one another.

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