公开(公告)号：US10261909B2

公开(公告)日：2019-04-16

申请号：US14811543

申请日：2015-07-28

Applicant: Intel Corporation

Inventor： James E. McCormick, Jr.

IPC: G06F12/08 ,  G06F12/0875 ,  G06F12/0893 ,  G06F13/40 ,  G06F9/30 ,  G06F9/38 ,  G06F12/0862

Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing a speculative cache modification design. For example, in one embodiment, such means may include an integrated circuit having a data bus; a cache communicably interfaced with the data bus; a pipeline communicably interfaced with the data bus, in which the pipeline is to receive a store instruction corresponding to a cache line to be written to cache; caching logic to perform a speculative cache write of the cache line into the cache before the store instruction retires from the pipeline; and cache line validation logic to determine if the cache line written into the cache is valid or invalid, in which the cache line validation logic is to invalidate the cache line speculatively written into the cache when determined invalid and further in which the store instruction is allowed to retire from the pipeline when the cache line is determined to be valid.

公开(公告)号：US11641326B2

公开(公告)日：2023-05-02

申请号：US16549915

申请日：2019-08-23

Applicant: Intel Corporation

Inventor： Karl S. Papadantonakis ,  Robert Southworth ,  Arvind Srinivasan ,  Helia A. Naeimi ,  James E. McCormick, Jr. ,  Jonathan Dama ,  Ramakrishna Huggahalli ,  Roberto Penaranda Cebrian

IPC: H04L49/103 ,  H04L47/625 ,  H04L47/6275 ,  H04L49/00 ,  H04L67/101 ,  H04L7/10 ,  H04L67/10

Abstract: Examples are described herein that relate to a mesh in a switch fabric. The mesh can include one or more buses that permit operations (e.g., read, write, or responses) to continue in the same direction, drop off to a memory, drop off a bus to permit another operation to use the bus, or receive operations that are changing direction. A latency estimate can be determined at least for operations that drop off from a bus to permit another operation to use the bus or receive and channel operations that are changing direction. An operation with a highest latency estimate (e.g., time of traversing a mesh) can be permitted to use the bus, even causing another operation, that is not to change direction, to drop off the bus and re-enter later.

公开(公告)号：US10346177B2

公开(公告)日：2019-07-09

申请号：US15378878

申请日：2016-12-14

Applicant: Intel Corporation

Inventor： Mahesh S. Natu ,  Wei Chen ,  Jing Ling ,  James E. McCormick, Jr.

IPC: G06F9/44 ,  G06F9/4401 ,  G06F11/10

Abstract: An embodiment of a memory apparatus may include a system memory, and a memory manager communicatively coupled to the system memory to determine a first amount of system memory needed for a boot process, initialize the first amount of system memory, start the boot process, and initialize additional system memory in parallel with the boot process. Other embodiments are disclosed and claimed.