公开(公告)号：US20180172759A1

公开(公告)日：2018-06-21

申请号：US15385500

申请日：2016-12-20

Applicant: Intel Corporation

Inventor： Lakshminarayana PAPPU ,  James J. GREALISH

IPC: G01R31/28 ,  H03K5/24

CPC classification number: G01R31/2853 ,  G01R31/31715 ,  G11C29/022 ,  G11C29/025 ,  G11C29/028 ,  H03K5/24

Abstract: A method and apparatus for platform component interconnect testing is disclosed. In one embodiment, an integrated circuit comprises: a plurality of interface circuitries, wherein each interface circuitry comprises a driver with adjustable pullup and pulldown resistances and having a driver output to output a driver voltage to a pad during test mode, and a comparator having a first input coupled to the driver output and a second input coupled to a voltage reference, the comparator being operable to generate a comparator output in response to comparing the driver voltage with the voltage reference; and analysis circuitry coupled to receive the comparator output, the analysis circuitry operable, during the test mode, to detect existence of a fault associated with a signal path coupled to the pad for each interface circuitry.

公开(公告)号：US20180276094A1

公开(公告)日：2018-09-27

申请号：US15468523

申请日：2017-03-24

Applicant: Intel Corporation

Inventor： Lakshminarayana PAPPU ,  James J. GREALISH

IPC: G06F11/22

CPC classification number: G06F11/2221

Abstract: Embodiments are generally directed to maintaining IO block operation in electronic systems for board testing. An embodiment of a system includes a processor; a power management block for the system; a plurality of IO (input/output) blocks; a read only memory for storage of firmware for the processor. The system is to provide support for a board-level test of the system including testing of one or more IO blocks of the plurality of IO blocks; and the firmware includes elements to stall a reset sequence of the system including the system branching to a mode that maintains power to the one or more IO blocks.