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    MAINTAINING IO BLOCK OPERATION IN ELECTRONIC SYSTEMS FOR BOARD TESTING
    1.
    发明申请
    MAINTAINING IO BLOCK OPERATION IN ELECTRONIC SYSTEMS FOR BOARD TESTING 审中-公开

    公开(公告)号：US20180276094A1

    公开(公告)日：2018-09-27

    申请号：US15468523

    申请日：2017-03-24

    Applicant: Intel Corporation

    Inventor： Lakshminarayana PAPPU ,  James J. GREALISH

    IPC: G06F11/22

    CPC classification number: G06F11/2221

    Abstract: Embodiments are generally directed to maintaining IO block operation in electronic systems for board testing. An embodiment of a system includes a processor; a power management block for the system; a plurality of IO (input/output) blocks; a read only memory for storage of firmware for the processor. The system is to provide support for a board-level test of the system including testing of one or more IO blocks of the plurality of IO blocks; and the firmware includes elements to stall a reset sequence of the system including the system branching to a mode that maintains power to the one or more IO blocks.

    PLATFORM DEBUG AND TESTING WITH SECURED HARDWARE
    2.
    发明申请
    PLATFORM DEBUG AND TESTING WITH SECURED HARDWARE 审中-公开

    公开(公告)号：US20190042382A1

    公开(公告)日：2019-02-07

    申请号：US15857535

    申请日：2017-12-28

    Applicant: Intel Corporation

    Inventor： Lakshminarayana PAPPU ,  Navneet DOUR ,  Christopher E. COX

    IPC: G06F11/273 ,  G06F11/27 ,  G06F9/448

    Abstract: A system includes test control circuitry in parallel with power control circuitry. The power control circuitry enables a core processor and memory interface drivers responsive to a reset. The test control circuitry can enable the memory interface drivers separately from the core processor to enable testing of the connections to the memory devices. The test control circuitry is triggered separately from the other power control circuitry, and can be protected to allow only secured access for testing.

    DEVICE, SYSTEM AND METHOD FOR PACKET PROCESSING TO FACILITATE CIRCUIT TESTING
    3.
    发明申请
    DEVICE, SYSTEM AND METHOD FOR PACKET PROCESSING TO FACILITATE CIRCUIT TESTING 审中-公开

    公开(公告)号：US20180285310A1

    公开(公告)日：2018-10-04

    申请号：US15476506

    申请日：2017-03-31

    Applicant: Intel Corporation

    Inventor： Lakshminarayana PAPPU ,  Suketu BHATT ,  Satheesh CHELLAPPAN

    IPC: G06F13/42 ,  G06F11/22

    CPC classification number: G06F13/4291

    Abstract: Techniques and mechanisms to modify packet information in support of on-chip test functionality. In an embodiment, an integrated circuit (IC) chip includes a protocol stack to receive and process packetized information—e.g., where the processing of at least one isochronous timestamp packet (ITP) includes circuitry of the protocol stack replacing non-deterministic data of the ITP with substitute information. A deterministic nature of the substitute information enables the subsequent generation of corresponding signature information which can be used in an evaluation of circuit performance. In another embodiment, the ITP packet is modified at a transaction layer of the protocol stack, and the signature information is determined with an accumulator circuit which is part of another layer of the protocol stack.

    DEVICE, SYSTEM AND METHOD FOR ON-CHIP TESTING OF PROTOCOL STACK CIRCUITRY
    4.
    发明申请
    DEVICE, SYSTEM AND METHOD FOR ON-CHIP TESTING OF PROTOCOL STACK CIRCUITRY 审中-公开

    公开(公告)号：US20180285305A1

    公开(公告)日：2018-10-04

    申请号：US15476513

    申请日：2017-03-31

    Applicant: Intel Corporation

    Inventor： Lakshminarayana PAPPU ,  Yonah LASKER

    IPC: G06F13/42 ,  G06F13/36 ,  G06F13/40

    CPC classification number: G06F13/42 ,  G06F13/36 ,  G06F13/4022

    Abstract: Techniques and mechanisms for providing test functionality at an integrated circuit (IC) chip. In an embodiment, the IC chip includes protocol stacks variously coupled each between a switch fabric and other switch circuitry which is configurable to selectively implement, at least in part, either of an operational mode and a test mode. The operational mode facilitates communication, via the switch circuitry, between a first protocol stack and physical layer circuitry. The test mode instead enables communication, between the first protocol stack and a second protocol stack, of test packet information which is based on a test packet received from the switch fabric. In another embodiment, the protocol stacks support communication according to a Thunderbolt™ protocol.

    DYNAMICALLY PROGRAMMABLE MEMORY TEST TRAFFIC ROUTER
    6.
    发明申请
    DYNAMICALLY PROGRAMMABLE MEMORY TEST TRAFFIC ROUTER 审中-公开

    公开(公告)号：US20190042131A1

    公开(公告)日：2019-02-07

    申请号：US15940499

    申请日：2018-03-29

    Applicant: Intel Corporation

    Inventor： Lakshminarayana PAPPU ,  Christopher E. COX ,  Navneet DOUR ,  Asaf RUBINSTEIN ,  Israel DIAMAND

    IPC: G06F3/06 ,  G06F12/0888 ,  G06F13/16 ,  G06F13/42

    Abstract: In a computer system, a multilevel memory includes a near memory device and a far memory device, which are byte addressable. The multilevel memory includes a controller that receives a data request including original tag information. The controller includes routing hardware to selectively provide alternate tag information for the data request to cause a cache hit or a cache miss to selectively direct the request to the near memory device or to the far memory device, respectively. The controller can include selection circuitry to select between the original tag information and the alternate tag information to control where the data request is sent.

    PHASE LOCK LOOP BYPASS FOR BOARD-LEVEL TESTING OF SYSTEMS
    7.
    发明申请
    PHASE LOCK LOOP BYPASS FOR BOARD-LEVEL TESTING OF SYSTEMS 审中-公开

    公开(公告)号：US20180275736A1

    公开(公告)日：2018-09-27

    申请号：US15468527

    申请日：2017-03-24

    Applicant: Intel Corporation

    Inventor： Lakshminarayana PAPPU ,  Baruch SCHNARCH

    IPC: G06F1/32 ,  H03L7/099 ,  G06F13/42

    CPC classification number: G06F1/3203 ,  G06F13/42 ,  G06F2213/0012 ,  H03L7/0995

    Abstract: Embodiments are generally directed to phase lock loop bypass for board level testing of systems. An embodiment of system includes a power management block for the system; multiple IO (input/output) blocks; a phase lock loop (PLL) block for each of the IO blocks, each of the phase lock loop blocks being switchable between providing an output of a PLL clock signal or providing a replacement clock signal as clocking for the respective IO block; and a read only memory for storage of firmware. In some embodiments, the firmware includes elements to enable operation of the plurality of IO blocks utilizing replacement clocking.

    PLATFORM COMPONENT INTERCONNECT TESTING
    8.
    发明申请
    PLATFORM COMPONENT INTERCONNECT TESTING 审中-公开

    公开(公告)号：US20180172759A1

    公开(公告)日：2018-06-21

    申请号：US15385500

    申请日：2016-12-20

    Applicant: Intel Corporation

    Inventor： Lakshminarayana PAPPU ,  James J. GREALISH

    IPC: G01R31/28 ,  H03K5/24

    CPC classification number: G01R31/2853 ,  G01R31/31715 ,  G11C29/022 ,  G11C29/025 ,  G11C29/028 ,  H03K5/24

    Abstract: A method and apparatus for platform component interconnect testing is disclosed. In one embodiment, an integrated circuit comprises: a plurality of interface circuitries, wherein each interface circuitry comprises a driver with adjustable pullup and pulldown resistances and having a driver output to output a driver voltage to a pad during test mode, and a comparator having a first input coupled to the driver output and a second input coupled to a voltage reference, the comparator being operable to generate a comparator output in response to comparing the driver voltage with the voltage reference; and analysis circuitry coupled to receive the comparator output, the analysis circuitry operable, during the test mode, to detect existence of a fault associated with a signal path coupled to the pad for each interface circuitry.

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