公开(公告)号：US20180095910A1

公开(公告)日：2018-04-05

申请号：US15283396

申请日：2016-10-01

Applicant: Intel Corporation

Inventor： Stanley Steve KULICK ,  Bezan KAPADIA ,  James SHEHADI ,  Amir Ali RADJAI

IPC: G06F13/16 ,  G06F13/40

CPC classification number: G06F13/1689 ,  G06F13/1673 ,  G06F13/4068

Abstract: A clock domain crossing can occur earlier in time by detection of when a data signal will coincide with a TSV (time slot valid) signal but the valid signal associated with the data signal will not coincide with a TSV. In response to such a detection, the domain crossing circuit can send the valid signal early, resulting in a valid signal sent on an earlier TSV and the data signal sent on a TSV. In one embodiment, such a system can cause a data signal to be received in a slower clock domain on a first edge of the slower clock signal after the data is queued in the faster clock domain. The sending of the early valid indication can reduce latency in transferring data between clock domains.