公开(公告)号：US09940984B1

公开(公告)日：2018-04-10

申请号：US15278802

申请日：2016-09-28

Applicant: Intel Corporation

Inventor： MD Altaf Hossain ,  Nagi Aboulenein ,  Jayapratap Bharathan

IPC: G11C7/10 ,  G06F13/16 ,  G11C8/18

CPC classification number: G11C7/1072 ,  G06F13/1684 ,  G11C5/04 ,  G11C7/1012 ,  G11C8/18

Abstract: A shared command/address (C/A) bus for memory devices in a multi-channel configuration can enable reducing the number of pins and signal lines in a memory subsystem. In one embodiment, a memory controller includes hardware logic to generate commands to access a plurality of memory devices via a plurality of channels and input/output (I/O) circuitry to transmit command/address (C/A) information for the commands to the plurality of memory devices over a single C/A bus for the plurality of channels. In one embodiment, double-speed strobe signal lines can also enable reducing the number of pins and signal lines in a memory subsystem.