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公开(公告)号:US11018054B2
公开(公告)日:2021-05-25
申请号:US16486612
申请日:2017-04-12
Applicant: Intel Corporation
Inventor: Daniel J. Zierath , Flavio Griggio , John D. Brooks
IPC: H01L21/76 , H01L27/06 , H01L21/768 , H01L21/321 , H01L23/532
Abstract: Disclosed herein are integrated circuit (IC) interconnects, as well as related devices and methods. For example, in some embodiments, an interconnect may include a first material and a second material distributed in the first material. A concentration of the second material may be greater proximate to the top surface than proximate to the bottom surface.
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公开(公告)号:US20200013673A1
公开(公告)日:2020-01-09
申请号:US16486612
申请日:2017-04-12
Applicant: Intel Corporation
Inventor: Daniel J. Zierath , Flavio Griggio , John D. Brooks
IPC: H01L21/768 , H01L23/532 , H01L21/321 , H01L27/06
Abstract: Disclosed herein are integrated circuit (IC) interconnects, as well as related devices and methods. For example, in some embodiments, an interconnect may include a first material and a second material distributed in the first material. A concentration of the second material may be greater proximate to the top surface than proximate to the bottom surface.
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公开(公告)号:US10483160B2
公开(公告)日:2019-11-19
申请号:US15745235
申请日:2015-09-23
Applicant: Intel Corporation
Inventor: Jeffery D. Bielefeld , Manish Chandhok , Asad Iqbal , John D. Brooks
IPC: H01L21/768 , H01L21/764 , H01L23/532 , H01L21/02
Abstract: A helmet layer is deposited on a plurality of conductive features on a first dielectric layer on a substrate. A second dielectric layer is deposited on a first portion of the helmet layer. An etch stop layer is deposited on a second portion the helmet layer.
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