公开(公告)号：US20190102500A1

公开(公告)日：2019-04-04

申请号：US15721195

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Byron Sinclair ,  John Freeman

IPC: G06F17/50 ,  G06F9/45 ,  G06F9/445

Abstract: Methods and apparatus for performing profile-guided optimization of integrated circuit hardware are provided. Circuit design tools may receive a source code and compile the source code to generate a hardware description. The hardware description may include profiling blocks configured to measure useful information required for optimization. The hardware description may then be simulated to gather profiling data. The circuit design tools may then analyze the gathered profiling data to identify additional opportunities for hardware optimization. The source code may then be modified based on the analysis of the profiling data to produce a smaller and faster hardware that is better suited to the application.

公开(公告)号：US20220197610A1

公开(公告)日：2022-06-23

申请号：US17692413

申请日：2022-03-11

Applicant: Intel Corporation

Inventor： Michael Kinsner ,  John Freeman ,  Ben J. Ashbaugh ,  Rajesh Poornachandran

IPC: G06F8/41 ,  G06F9/54

Abstract: An apparatus to facilitate incremental just-in-time (JIT) performance refinement for programmable logic device offload is disclosed. The apparatus includes a processor to: initiate multiple just-in-time (JIT) compilation iterations of an application; program a first architecture of a first compilation of the multiple JIT compilation iterations to a programmable logic device and execute the application on the first architecture, wherein the first compilation comprises a faster compilation time amongst the multiple JIT compilation iterations; identify a hotspot; determine that a second compilation of the multiple JIT compilation iterations is complete, wherein the second compilation comprises a slower compilation time than the first compilation; and program a second architecture of the second compilation of the multiple JIT compilation iterations to the programmable logic device and execute the application on the second architecture.

公开(公告)号：US20230342531A1

公开(公告)日：2023-10-26

申请号：US18311886

申请日：2023-05-03

Applicant: Intel Corporation

Inventor： Byron Sinclair ,  John Freeman

IPC: G06F30/39 ,  G06F8/41 ,  G06F30/20

CPC classification number: G06F30/39 ,  G06F8/41 ,  G06F8/4434 ,  G06F30/20 ,  G06F8/65

Abstract: Methods and apparatus for performing profile-guided optimization of integrated circuit hardware are provided. Circuit design tools may receive a source code and compile the source code to generate a hardware description. The hardware description may include profiling blocks configured to measure useful information required for optimization. The hardware description may then be simulated to gather profiling data. The circuit design tools may then analyze the gathered profiling data to identify additional opportunities for hardware optimization. The source code may then be modified based on the analysis of the profiling data to produce a smaller and faster hardware that is better suited to the application.

公开(公告)号：US11675948B2

公开(公告)日：2023-06-13

申请号：US15721195

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Byron Sinclair ,  John Freeman

IPC: G06F9/44 ,  G06F9/445 ,  G06F9/455 ,  G06F30/39 ,  G06F8/41 ,  G06F30/20 ,  G06F8/65 ,  G06F111/06 ,  G06F117/08

CPC classification number: G06F30/39 ,  G06F8/41 ,  G06F8/4434 ,  G06F30/20 ,  G06F8/65 ,  G06F2111/06 ,  G06F2117/08

Abstract: Methods and apparatus for performing profile-guided optimization of integrated circuit hardware are provided. Circuit design tools may receive a source code and compile the source code to generate a hardware description. The hardware description may include profiling blocks configured to measure useful information required for optimization. The hardware description may then be simulated to gather profiling data. The circuit design tools may then analyze the gathered profiling data to identify additional opportunities for hardware optimization. The source code may then be modified based on the analysis of the profiling data to produce a smaller and faster hardware that is better suited to the application.

公开(公告)号：US20220197613A1

公开(公告)日：2022-06-23

申请号：US17692405

申请日：2022-03-11

Applicant: Intel Corporation

Inventor： Michael Kinsner ,  Rajesh Poornachandran ,  John Freeman

IPC: G06F8/41

Abstract: An apparatus to facilitate clock gating and clock scaling based on runtime application task graph information is disclosed. The apparatus includes a processor to: receive, from a compiler, a bitstream generated from code of an application, the bitstream related to a workload of the application; generate a task graph of the application using at least part of the bitstream, the task graph to represent one of a relationship and dependency of the code; program the bitstream to an accelerator device, wherein the bitstream to configure the accelerator device to support the workload of the application; execute one or more kernels of the code using the accelerator device; identify one or more optimizations for the accelerator device based on the task graph of the application; and transmit a command to cause the one or more optimizations to be implemented in the at least one region of the accelerator device.