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公开(公告)号：US20200313694A1
公开(公告)日：2020-10-01
申请号：US16367511
申请日：2019-03-28
Applicant: Intel Corporation
Inventor： Wei Wu , Vivek Kozihikkottu , Dinesh Somasekhar , Jon Stephan , Kon-Woo Kwon
Abstract: In an embodiment, a processor includes error correction code (ECC) circuitry to: receive a codeword comprising data bits and parity bits; generate, using a parity checking matrix H, a syndrome vector associated with the received codeword, where the parity-checking matrix H comprises a data segment comprising N data columns and a parity segment comprising K parity columns, where a total quantity of data columns in the data segment with even weight is equal to N+K−2(K−1)+1; and detect an adjacent two bit error in the codeword based on a comparison of the syndrome vector to the parity checking matrix H. Other embodiments are described and claimed.
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公开(公告)号：US10884853B2
公开(公告)日：2021-01-05
申请号：US16249631
申请日：2019-01-16
Applicant: Intel Corporation
Inventor： Wei Wu , Dinesh Somasekhar , Jon Stephan , Aravinda K. Radhakrishnan , Vivek Kozhikkottu
Abstract: An apparatus includes a binary content addressable memory (BCAM) to store a plurality of error protection code (ECC) generated codewords (CWs), the BCAM divided into segments (sub-BCAMs), wherein the sub-BCAMs are to respectively store pre-defined first portions of the CWs, and to store corresponding second portions of a search word. In embodiments, the apparatus further includes logic circuitry, to obtain partial match results between the first portions of the CWs and corresponding second portions of the search word, and identify one or more CWs of the plurality of CWs that match the search word, based at least in part on the partial match results, wherein the match indicates that data included in the one or more CW is the same as the data included in the search word.
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公开(公告)号：US20190146873A1
公开(公告)日：2019-05-16
申请号：US16249631
申请日：2019-01-16
Applicant: Intel Corporation
Inventor： Wei Wu , Dinesh Somasekhar , Jon Stephan , Aravinda K. Radhakrishnan , Vivek Kozhikkottu
Abstract: An apparatus includes a binary content addressable memory (BCAM) to store a plurality of error protection code (ECC) generated codewords (CWs), the BCAM divided into segments (sub-BCAMs), wherein the sub-BCAMs are to respectively store pre-defined first portions of the CWs, and to store corresponding second portions of a search word. In embodiments, the apparatus further includes logic circuitry, to obtain partial match results between the first portions of the CWs and corresponding second portions of the search word, and identify one or more CWs of the plurality of CWs that match the search word, based at least in part on the partial match results, wherein the match indicates that data included in the one or more CW is the same as the data included in the search word.
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