公开(公告)号：US20240219452A1

公开(公告)日：2024-07-04

申请号：US18090422

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Prasoon JOSHI ,  Joseph BASILE ,  Eric BRUMMER ,  Evan FLEDELL ,  Joshua FREIER ,  Brett GROSSMAN ,  Jennifer HUENING ,  Matthew KIRSCH ,  James NEEB ,  Robert NESTING ,  Charles PETERSON ,  Ashraf REZAIE ,  Ling Hong TAN ,  Xianghong TONG ,  Vladimir VLASYUK

IPC: G01R31/28 ,  G01R1/07

CPC classification number: G01R31/2834 ,  G01R1/071 ,  G01R31/2863

Abstract: The disclosure is directed to a device interface, system and method for connecting a Tester Interface Unit (TIU) to an automated test equipment that enable data rates of over 1.0 Gbps over scalable high speed cables. The device interface includes at least one flange assembly connecting an electron beam probe (EBP) in a vacuum-controlled environment to an ambient environment, the flange assembly including a vacuum-controlled passthrough environment coupled to the EBP, a plurality of cables coupled to a plurality of connectors within the vacuum-controlled passthrough environment to provide power, control and signal connections to the ambient environment, the plurality cables including plurality of hermetically-sealed printed circuit boards (PCBs) carrying digital high speed signals from the TIU, a plurality of power cables supporting a plurality of power requirements, and a plurality of ATE communication control cables to direct the TIU.

公开(公告)号：US20240103073A1

公开(公告)日：2024-03-28

申请号：US17952031

申请日：2022-09-23

Applicant: Intel Corporation

Inventor： Patrick PARDY ,  Robert WADELL ,  Tewodros WONDIMU ,  Michael APODACA ,  Joshua FREIER ,  Amir RAVEH ,  Eric BRUMMER

IPC: G01R31/307 ,  H01L23/467

CPC classification number: G01R31/307 ,  H01L23/467

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for an enclosure, which may be referred to as a cartridge, that surrounds a semiconductor device prior to the semiconductor device being bombarded with an electron beam during operational testing. In embodiments, the enclosure may include a cooling plate that includes a thermal cooling mechanism that is thermally coupled with the semiconductor device to control the temperature of the semiconductor device during testing. The thermal cooling mechanism may include a manifold that extends through the plate through which a cooled fluid, cooled air, or some other cool material may be circulated to cool the semiconductor device. Other embodiments may be described and/or claimed.