公开(公告)号：US20210374848A1

公开(公告)日：2021-12-02

申请号：US17401575

申请日：2021-08-13

Applicant: Intel Corporation

Inventor： Andrew HERDRICH ,  Edwin VERPLANKE ,  Ravishankar IYER ,  Christopher GIANOS ,  Jeffrey D. CHAMBERLAIN ,  Ronak SINGH ,  Julius MANDELBLAT ,  Bret Toll

IPC: G06Q40/02 ,  G06F12/0875 ,  G06F12/0897

Abstract: Systems, methods, and apparatuses for resource bandwidth monitoring and control are described. For example, in some embodiments, an apparatus comprising a requestor device to send a credit based request, a receiver device to receive and consume the credit based request, and a delay element in a return path between the requestor and receiver devices, the delay element to delay a credit based response from the receiver to the requestor are detailed.

公开(公告)号：US20180189192A1

公开(公告)日：2018-07-05

申请号：US15394550

申请日：2016-12-29

Applicant: INTEL CORPORATION

Inventor： Israel DIAMAND ,  Zvika GREENFIELD ,  Julius MANDELBLAT ,  Asaf RUBINSTEIN

IPC: G06F12/12 ,  G06F12/0891 ,  G06F12/0864 ,  G06F12/0893

CPC classification number: G06F12/0893 ,  G06F12/0864 ,  G06F12/0884 ,  G06F12/0897 ,  G06F12/128 ,  G06F2212/1024 ,  G06F2212/507 ,  G06F2212/608

Abstract: An apparatus is described. The apparatus includes a memory controller to interface to a multi-level system memory having first and second different cache structures. The memory controller has circuitry to service a read request by concurrently performing a look-up into the first and second different cache structures for a cache line that is targeted by the read request.