公开(公告)号：US20240243913A1

公开(公告)日：2024-07-18

申请号：US18560368

申请日：2021-11-23

Applicant: Intel Corporation

Inventor： Junyuan WANG ,  Kapil SOOD ,  Brian WILL ,  Thomas Joseph O'DWYER ,  Zijuan FAN ,  Kaijie GUO ,  Maksim LUKOSHKOV ,  Seosamh O'RIORDAIN ,  Jun XU ,  Guodong ZHU ,  Siming WAN

IPC: H04L9/30

CPC classification number: H04L9/3066 ,  H04L9/302

Abstract: Methods and apparatus for customers key protection for cloud native deployments. Compute resources for a compute platform comprising platform hardware including one or more processors are allocated to one or more customers that use the compute resources to execute applications and/or services used to perform customer workloads. The compute platform includes a per-part device key that is used to generate hardware protected key used by the applications and services. Mechanisms are provided to ensure hardware protected keys can only be accessed by associated customers and/or customer applications and services, while preventing other customers and/or applications and services from accessing the hardware protected keys. The hardware protected keys include keys employing various forms of RSA and ECC Wrapped Private Keys (WPKs) including RSA WPKs, RSA Chinese Remainder Theorem CRT WPK and ECC WPKs.

公开(公告)号：US20240241831A1

公开(公告)日：2024-07-18

申请号：US18622745

申请日：2024-03-29

Applicant: Intel Corporation

Inventor： Junyuan WANG ,  Haoxiang SUN ,  Xin ZENG ,  Maksim LUKOSHKOV ,  Weigang LI ,  Zijuan FAN ,  Jun XU

IPC: G06F12/0862

CPC classification number: G06F12/0862 ,  G06F2212/602

Abstract: Techniques to reduce data processing latency for a device. Circuitry at a device coupled with a host processor can facilitate execution of parallel tasks associated with processing data for a service offloaded to the device from the host processor. The parallel tasks can include prefetching information for address translations related to a shared virtual memory (SVM) space that is shared between the device and the host processor and prefetching data to be processed by device in relation to the offloaded service.

公开(公告)号：US20210272638A1

公开(公告)日：2021-09-02

申请号：US17253095

申请日：2018-12-25

Applicant: Intel Corporation

Inventor： Chunyuan HOU ,  Ke LIANG ,  Jun XU ,  Si LI

IPC: G11C16/34 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/08

Abstract: A storage array includes multiple wordlines of storage cells that can be selectively charged to an erase voltage or an inhibit voltage. Control logic associated with the storage array can perform erase verify in stages. On a first erase verify pass, the control logic can set wordlines of an erase block or subblock to a first erase voltage. On a second erase verify pass, the control logic can trigger a second erase verify pulse and set passing wordlines to an inhibit voltage, and failing wordlines to a second erase voltage higher than the first voltage. Inhibiting the already passing wordlines can reduce threshold voltage differences among the wordlines.