公开(公告)号：US20250006592A1

公开(公告)日：2025-01-02

申请号：US18217208

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Ming-Yi Shen ,  Chi-Hing Choi ,  Jaladhi Mehta ,  Tofizur Rahman ,  Payam Amin ,  Justin E. Mueller ,  Vincent Hipwell ,  Cortnie S. Vogelsberg ,  Shivani Falgun Patel

IPC: H01L23/48 ,  H01L21/768 ,  H01L27/088

Abstract: Techniques to form low-resistance vias are discussed. In an example, semiconductor devices of a given row each include a semiconductor region extending in a first direction between corresponding source or drain regions, and a gate structure extending in a second direction over the semiconductor regions. Any semiconductor device may be separated from an adjacent semiconductor device along the second direction by a dielectric structure, through which a via passes. The via may include a conductive portion that extends through a dielectric wall in a third direction along at least an entire thickness of the gate structure. The conductive portion includes a conductive liner directly on the dielectric wall and a conductive fill on the conductive liner. The conductive liner comprises a pure elemental metal, such as tungsten, molybdenum, ruthenium, or a nickel aluminum alloy, with no metal nitride or barrier layer present between the conductive liner and the dielectric wall.