-
公开(公告)号:US20250132245A1
公开(公告)日:2025-04-24
申请号:US18491111
申请日:2023-10-20
Applicant: Intel Corporation
Inventor: Tofizur RAHMAN , Conor P. Puls , Payam Amin , Santhosh Koduri , Clay Mortensen , Bozidar Marinkovic , Shivani Falgun Patel , Richard Bonsu , Jaladhi Mehta , Dincer Unluer
IPC: H01L23/522 , H01L23/528 , H01L23/532
Abstract: A fabrication method and associated integrated circuit (IC) structures and devices that include one or more self-insulated vias is described herein. In one example, an IC structure includes a via surrounded by an insulator material and a layer of insulator material between a conductive material of the via and the surrounding insulator material. In one example, the layer of insulator material has one or more material properties that are different than the surrounding insulator material, including one or more of a different density, a different dielectric constant, and a different material composition.
-
公开(公告)号:US20250006592A1
公开(公告)日:2025-01-02
申请号:US18217208
申请日:2023-06-30
Applicant: Intel Corporation
Inventor: Ming-Yi Shen , Chi-Hing Choi , Jaladhi Mehta , Tofizur Rahman , Payam Amin , Justin E. Mueller , Vincent Hipwell , Cortnie S. Vogelsberg , Shivani Falgun Patel
IPC: H01L23/48 , H01L21/768 , H01L27/088
Abstract: Techniques to form low-resistance vias are discussed. In an example, semiconductor devices of a given row each include a semiconductor region extending in a first direction between corresponding source or drain regions, and a gate structure extending in a second direction over the semiconductor regions. Any semiconductor device may be separated from an adjacent semiconductor device along the second direction by a dielectric structure, through which a via passes. The via may include a conductive portion that extends through a dielectric wall in a third direction along at least an entire thickness of the gate structure. The conductive portion includes a conductive liner directly on the dielectric wall and a conductive fill on the conductive liner. The conductive liner comprises a pure elemental metal, such as tungsten, molybdenum, ruthenium, or a nickel aluminum alloy, with no metal nitride or barrier layer present between the conductive liner and the dielectric wall.
-