公开(公告)号：US20250098249A1

公开(公告)日：2025-03-20

申请号：US18467859

申请日：2023-09-15

Applicant: Intel Corporation

Inventor： Avijit Barik ,  Tao Chu ,  Minwoo Jang ,  Tofizur RAHMAN ,  Conor P. Puls ,  Ariana E. Bondoc ,  Diane Lancaster ,  Chi-Hing Choi ,  Derek Keefer

IPC: H01L29/45 ,  H01L21/285 ,  H01L23/522 ,  H01L23/532 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: Disclosed herein are IC structures and devices that aim to mitigate proximity effects of deep trench vias. An example IC structure may include a device region having a first face and a second face, the second face being opposite the first face, and further include a conductive via extending between the first face and the second face, wherein the conductive via includes an electrically conductive material, and wherein a concentration of titanium at sidewalls of the conductive via is below about 1015 atoms per cubic centimeter.

公开(公告)号：US20240006488A1

公开(公告)日：2024-01-04

申请号：US17856620

申请日：2022-07-01

Applicant: Intel Corporation

Inventor： Nazila Haratipour ,  Gilbert Dewey ,  Nancy Zelick ,  Siddharth Chouksey ,  I-Cheng Tung ,  Arnab Sen Gupta ,  Jitendra Kumar Jha ,  David Kohen ,  Natalie Briggs ,  Chi-Hing Choi ,  Matthew V. Metz ,  Jack T. Kavalieros

IPC: H01L29/08 ,  H01L27/088 ,  H01L29/417 ,  H01L29/78 ,  H01L29/40 ,  H01L29/66 ,  H01L21/033

CPC classification number: H01L29/0847 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/7851 ,  H01L29/401 ,  H01L29/66795 ,  H01L21/0332

Abstract: In one embodiment, layers comprising Carbon (e.g., Silicon Carbide) are on source/drain regions of a transistor, e.g., before gate formation and metallization, and the layers comprising Carbon are later removed in the manufacturing process to form electrical contacts on the source/drain regions.

公开(公告)号：US20240006494A1

公开(公告)日：2024-01-04

申请号：US17856206

申请日：2022-07-01

Applicant: Intel Corporation

Inventor： Nazila Haratipour ,  Gilbert Dewey ,  Nancy Zelick ,  Siddharth Chouksey ,  I-Cheng Tung ,  Arnab Sen Gupta ,  Jitendra Kumar Jha ,  Chi-Hing Choi ,  Matthew V. Metz ,  Jack T. Kavalieros

IPC: H01L29/417 ,  H01L27/092 ,  H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L29/41733 ,  H01L27/0924 ,  H01L29/42392 ,  H01L29/0673 ,  H01L29/78618 ,  H01L29/78696 ,  H01L29/6656

Abstract: Semiconductor structures having a source and/or drain with a refractory metal cap, and methods of forming the same, are described herein. In one example, a semiconductor structure includes a channel, a gate, a source, and a drain. The source and drain contain silicon and germanium, and one or both of the source and drain are capped with a semiconductor cap and a refractory metal cap. The semiconductor cap is on the source and/or drain and contains germanium and boron. The refractory metal cap is on the semiconductor cap and contains a refractory metal.

公开(公告)号：US20240006506A1

公开(公告)日：2024-01-04

申请号：US17856979

申请日：2022-07-02

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Siddharth Chouksey ,  Nazila Haratipour ,  Christopher Jezewski ,  Jitendra Kumar Jha ,  Ilya V. Karpov ,  Jack T. Kavalieros ,  Arnab Sen Gupta ,  I-Cheng Tung ,  Nancy Zelick ,  Chi-Hing Choi ,  Dan S. Lavric

IPC: H01L29/45 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78 ,  H01L27/088

CPC classification number: H01L29/458 ,  H01L29/41733 ,  H01L29/41791 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/7851 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/401

Abstract: Contacts to n-type source/drain regions comprise a phosphide or arsenide metal compound layer. The phosphide or arsenide metal compound layers can aid in forming thermally stable low resistance contacts. A phosphide or arsenide metal compound layer is positioned between the source/drain region and the contact metal layer of the contact. A phosphide or arsenic metal compound layer can be used in contacts contacting n-type source/drain regions comprising phosphorous or arsenic as the primary dopant, respectively. The phosphide or arsenide metal compound layers prevent diffusion of phosphorous or arsenic from the source/drain region into the metal contact layer and dopant deactivation in the source/drain region due to annealing and other high-temperature processing steps that occur after contact formation. Phosphide and arsenide metal contact layers can also reduce the amount of silicide that forms in source/drain regions during processing by limiting the amount of contact metal that diffuses into source/drain regions.

公开(公告)号：US20220416032A1

公开(公告)日：2022-12-29

申请号：US17358436

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Debaleena Nandi ,  Chi-Hing Choi ,  Gilbert Dewey ,  Harold Kennel ,  Omair Saadat ,  Jitendra Kumar Jha ,  Adedapo Oni ,  Nazila Haratipour ,  Anand Murthy ,  Tahir Ghani

IPC: H01L29/417 ,  H01L27/088 ,  H01L29/161 ,  H01L21/8234 ,  H01L21/28 ,  H01L21/768

Abstract: Source and drain contacts that provide improved contact resistance and contact interface stability for transistors employing silicon and germanium source and drain materials, related transistor structures, integrated circuits, systems, and methods of fabrication are disclosed. Such source and drain contacts include a contact layer of co-deposited titanium and silicon on the silicon and germanium source and drain. The disclosed source and drain contacts improve transistor performance including switching speed and reliability.

公开(公告)号：US20250006592A1

公开(公告)日：2025-01-02

申请号：US18217208

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Ming-Yi Shen ,  Chi-Hing Choi ,  Jaladhi Mehta ,  Tofizur Rahman ,  Payam Amin ,  Justin E. Mueller ,  Vincent Hipwell ,  Cortnie S. Vogelsberg ,  Shivani Falgun Patel

IPC: H01L23/48 ,  H01L21/768 ,  H01L27/088

Abstract: Techniques to form low-resistance vias are discussed. In an example, semiconductor devices of a given row each include a semiconductor region extending in a first direction between corresponding source or drain regions, and a gate structure extending in a second direction over the semiconductor regions. Any semiconductor device may be separated from an adjacent semiconductor device along the second direction by a dielectric structure, through which a via passes. The via may include a conductive portion that extends through a dielectric wall in a third direction along at least an entire thickness of the gate structure. The conductive portion includes a conductive liner directly on the dielectric wall and a conductive fill on the conductive liner. The conductive liner comprises a pure elemental metal, such as tungsten, molybdenum, ruthenium, or a nickel aluminum alloy, with no metal nitride or barrier layer present between the conductive liner and the dielectric wall.

公开(公告)号：US20240105508A1

公开(公告)日：2024-03-28

申请号：US17935647

申请日：2022-09-27

Applicant: Intel Corporation

Inventor： Jitendra Kumar Jha ,  Justin Mueller ,  Nazila Haratipour ,  Gilbert W. Dewey ,  Chi-Hing Choi ,  Jack T. Kavalieros ,  Siddharth Chouksey ,  Nancy Zelick ,  Jean-Philippe Turmaud ,  I-Cheng Tung ,  Blake Bluestein

IPC: H01L21/768 ,  H01L29/49

CPC classification number: H01L21/76856 ,  H01L21/76837 ,  H01L21/76877 ,  H01L29/4908

Abstract: Disclosed herein are integrated circuit (IC) devices with contacts using nitridized molybdenum. For example, a contact arrangement for an IC device may include a semiconductor material and a contact extending into a portion of the semiconductor material. The contact may include molybdenum. The molybdenum may be in a first layer and a second layer, where the second layer may further include nitrogen. The first layer may have a thickness between about 5 nanometers and 16 nanometers, and the second layer may have a thickness between about 0.5 nanometers to 2.5 nanometers. The contact may further include a fill material (e.g., an electrically conductive material) and the second layer may be in contact with the fill material. The molybdenum may have a low resistance, and thus may improve the electrical performance of the contact. The nitridized molybdenum may prevent oxidation during the fabrication of the contact.

公开(公告)号：US20240006533A1

公开(公告)日：2024-01-04

申请号：US17856982

申请日：2022-07-02

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Siddharth Chouksey ,  Nazila Haratipour ,  Christopher Jezewski ,  Jitendra Kumar Jha ,  Ilya V. Karpov ,  Matthew V. Metz ,  Arnab Sen Gupta ,  I-Cheng Tung ,  Nancy Zelick ,  Chi-Hing Choi ,  Dan S. Lavric

IPC: H01L29/78 ,  H01L29/167

CPC classification number: H01L29/785 ,  H01L29/167

Abstract: Contacts to p-type source/drain regions comprise a boride, indium, or gallium metal compound layer. The boride, indium, or gallium metal compound layers can aid in forming thermally stable low resistance contacts. A boride, indium, or gallium metal compound layer is positioned between the source/drain region and the contact metal layer. A boride, indium, or gallium metal compound layer can be used in contacts contacting p-type source/drain regions comprising boron, indium, or gallium as the primary dopant, respectively. The boride, indium, or gallium metal compound layers prevent diffusion of boron, indium, or gallium from the source/drain region into the metal contact layer and dopant deactivation in the source/drain region due to annealing and other high-temperature processing steps that occur after contact formation. Boride, indium, or gallium metal contact layers can also reduce the amount of silicide that forms in source/drain regions during processing by limiting contact metal diffusion into source/drain regions.