公开(公告)号：US20230307449A1

公开(公告)日：2023-09-28

申请号：US17656490

申请日：2022-03-25

Applicant: Intel Corporation

Inventor： Tao Chu ,  Minwoo Jang ,  Aurelia Chi Wang ,  Conor Puls ,  Brian Greene ,  Tofizur Rahman ,  Lin Hu ,  Jaladhi Mehta ,  Chung-Hsun Lin ,  Walid Hafez

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L27/088 ,  H01L29/0665 ,  H01L29/42392

Abstract: An integrated circuit includes a first source region, a first drain region, a first fin having (i) a first upper region laterally between the first source region and the first drain region and (ii) a first lower region below the first upper region, and a first gate structure on at least top and side surfaces of the first upper region. The integrated circuit further includes a second source region, a second drain region, a second fin having (i) a second upper region laterally between the second source region and the second drain region and (ii) a second lower region below the second upper region, and a second gate structure on at least top and side surfaces of the second upper region. In an example, a first vertical height of the first lower region is different from a second vertical height of the second lower region by at least 2 nanometers (nm).

公开(公告)号：US20250132245A1

公开(公告)日：2025-04-24

申请号：US18491111

申请日：2023-10-20

Applicant: Intel Corporation

Inventor： Tofizur RAHMAN ,  Conor P. Puls ,  Payam Amin ,  Santhosh Koduri ,  Clay Mortensen ,  Bozidar Marinkovic ,  Shivani Falgun Patel ,  Richard Bonsu ,  Jaladhi Mehta ,  Dincer Unluer

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: A fabrication method and associated integrated circuit (IC) structures and devices that include one or more self-insulated vias is described herein. In one example, an IC structure includes a via surrounded by an insulator material and a layer of insulator material between a conductive material of the via and the surrounding insulator material. In one example, the layer of insulator material has one or more material properties that are different than the surrounding insulator material, including one or more of a different density, a different dielectric constant, and a different material composition.

公开(公告)号：US20240290835A1

公开(公告)日：2024-08-29

申请号：US18174007

申请日：2023-02-24

Applicant: Intel Corporation

Inventor： Chiao-Ti Huang ,  Guowei Xu ,  Tao Chu ,  Robin Chao ,  Jaladhi Mehta ,  Brian Greene ,  Chung-Hsun Lin

IPC: H01L29/06 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/40 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L21/823412 ,  H01L27/0886 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/78696

Abstract: Fabrication methods that employ an etch stop layer to assist subfin removal during fabrication of nanoribbon-based transistors are disclosed. An example fabrication method includes providing a stack of nanoribbons above a subfin, where the nanoribbons and the subfin include one or more semiconductor materials; depositing an etch stop layer over a top of the subfin and around portions of the nanoribbons; removing the etch stop layer from around the portions of the nanoribbons; providing a gate dielectric material around the portions of the nanoribbons and over the etch stop layer over the top of the subfin; depositing a gate electrode material around the portions of the nanoribbons; and performing an etch to remove the subfin without substantially removing the etch stop layer.

公开(公告)号：US20250107156A1

公开(公告)日：2025-03-27

申请号：US18471710

申请日：2023-09-21

Applicant: Intel Corporation

Inventor： Chiao-Ti Huang ,  Robin Chao ,  Jaladhi Mehta ,  Tao Chu ,  Guowei Xu ,  Ting-Hsiang Hung ,  Feng Zhang ,  Yang Zhang ,  Chia-Ching Lin ,  Chung-Hsun Lin ,  Anand Murthy

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66

Abstract: Techniques are provided herein to form an integrated circuit having dielectric material formed in cavities beneath source or drain regions. The cavities may be formed within subfin portions of semiconductor devices. In one such example, a FET (field effect transistor) includes a gate structure extending around a fin or any number of nanowires of semiconductor material. The semiconductor material may extend in a first direction between source and drain regions while the gate structure extends over the semiconductor material in a second direction substantially orthogonal to the first direction. A dielectric fill may be formed in a recess beneath the source or drain regions, or a dielectric liner may be formed on sidewalls of the recess, to prevent epitaxial growth of the source or drain regions from the subfins. Removal of the semiconductor subfin from the backside may then be performed without causing damage to the source or drain regions.

公开(公告)号：US20250006592A1

公开(公告)日：2025-01-02

申请号：US18217208

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Ming-Yi Shen ,  Chi-Hing Choi ,  Jaladhi Mehta ,  Tofizur Rahman ,  Payam Amin ,  Justin E. Mueller ,  Vincent Hipwell ,  Cortnie S. Vogelsberg ,  Shivani Falgun Patel

IPC: H01L23/48 ,  H01L21/768 ,  H01L27/088

Abstract: Techniques to form low-resistance vias are discussed. In an example, semiconductor devices of a given row each include a semiconductor region extending in a first direction between corresponding source or drain regions, and a gate structure extending in a second direction over the semiconductor regions. Any semiconductor device may be separated from an adjacent semiconductor device along the second direction by a dielectric structure, through which a via passes. The via may include a conductive portion that extends through a dielectric wall in a third direction along at least an entire thickness of the gate structure. The conductive portion includes a conductive liner directly on the dielectric wall and a conductive fill on the conductive liner. The conductive liner comprises a pure elemental metal, such as tungsten, molybdenum, ruthenium, or a nickel aluminum alloy, with no metal nitride or barrier layer present between the conductive liner and the dielectric wall.