公开(公告)号：US20180270948A1

公开(公告)日：2018-09-20

申请号：US15675883

申请日：2017-08-14

Applicant: Intel Corporation

Inventor： William L. Barber ,  Keith Pinson ,  Andrew P. Collins ,  Boping Wu ,  Isaac Ali ,  Colin L. Perry

IPC: H05K1/02 ,  H02H9/04 ,  H01L23/50

CPC classification number: H05K1/0231 ,  H01L23/50 ,  H01L2924/0002 ,  H02H9/04 ,  H05K1/025 ,  H05K2201/09672 ,  H01L2924/00

Abstract: In various embodiments, apparatuses and methods are disclosed that may be able to implement a multi-layer, three dimensional routing between a decoupling component and an input port for a SoC or MCM. A three dimensional (3D) structure may provide a defined current return path from the decoupling component to the input port. The current return path may be constrained by design to provide an equal and opposite electromagnetic flux to the input port thereby reducing series inductance between the input port and the decoupling component.

公开(公告)号：US10015878B2

公开(公告)日：2018-07-03

申请号：US14945762

申请日：2015-11-19

Applicant: Intel Corporation

Inventor： William L. Barber ,  Keith Pinson ,  Andrew P. Collins ,  Boping Wu ,  Isaac Ali ,  Colin L. Perry

IPC: H02H9/04 ,  H05K1/02 ,  H01L23/50

CPC classification number: H05K1/0231 ,  H01L23/50 ,  H01L2924/0002 ,  H02H9/04 ,  H05K1/025 ,  H05K2201/09672 ,  H01L2924/00

Abstract: In various embodiments, apparatuses and methods are disclosed that may be able to implement a multi-layer, three dimensional routing between a decoupling component and an input port for a SoC or MCM. A three dimensional (3D) structure may provide a defined current return path from the decoupling component to the input port. The current return path may be constrained by design to provide an equal and opposite electromagnetic flux to the input port thereby reducing series inductance between the input port and the decoupling component.

公开(公告)号：US09124229B2

公开(公告)日：2015-09-01

申请号：US13800811

申请日：2013-03-13

Applicant: Intel Corporation

Inventor： Viatcheslav I. Suetinov ,  Keith Pinson ,  Nicholas P. Cowley

IPC: H03F3/45

CPC classification number: H03F3/45237 ,  H03F3/189

Abstract: An amplifier, including a voltage-to-current converter (V2I) to control an output current based on an input voltage, resistive degeneration circuitry to reduce baseband gain of the voltage-to-current converter, capacitive degeneration circuitry to increase passband gain of the voltage-to-current converter, and impedance control circuitry to compensate for negative input impedance of the capacitive degeneration circuitry. The V2I may include series-connected complimentary V2Is. The impedance control circuitry may include resistive negative feedback to provide a real part of input impedance, which may increase a frequency range for which the amplifier is linear. Capacitive degeneration and associated phase compensation may increase a frequency range for which the resistive feedback is negative. The amplifier may be configured as a single-input/single-output system and/or as a differential system.

Abstract translation: 放大器，包括基于输入电压控制输出电流的电压 - 电流转换器（V2I），用于降低电压 - 电流转换器的基带增益的电阻退化电路，用于增加电压 - 电流转换器的通带增益 电压 - 电流转换器和阻抗控制电路，以补偿电容性退化电路的负输入阻抗。 V2I可能包括串联互补的V2I。 阻抗控制电路可以包括电阻性负反馈以提供输入阻抗的实部，其可以增加放大器为线性的频率范围。 电容退化和相关的相位补偿可能会增加电阻反馈为负的频率范围。 放大器可以被配置为单输入/单输出系统和/或差分系统。

公开(公告)号：US20160309580A1

公开(公告)日：2016-10-20

申请号：US14945762

申请日：2015-11-19

Applicant: Intel Corporation

Inventor： William L. Barber ,  Keith Pinson ,  Andrew P. Collins ,  Boping Wu ,  Isaac Ali ,  Colin L. Perry

IPC: H05K1/02 ,  H01L23/50

CPC classification number: H05K1/0231 ,  H01L23/50 ,  H01L2924/0002 ,  H02H9/04 ,  H05K1/025 ,  H05K2201/09672 ,  H01L2924/00

Abstract: In various embodiments, apparatuses and methods are disclosed that may be able to implement a multi-layer, three dimensional routing between a decoupling component and an input port for a SoC or MCM. A three dimensional (3D) structure may provide a defined current return path from the decoupling component to the input port. The current return path may be constrained by design to provide an equal and opposite electromagnetic flux to the input port thereby reducing series inductance between the input port and the decoupling component.

公开(公告)号：US09225164B2

公开(公告)日：2015-12-29

申请号：US14534979

申请日：2014-11-06

Applicant: Intel Corporation

Inventor： William L. Barber ,  Keith Pinson ,  Andrew P. Collins ,  Boping Wu ,  Isaac Ali ,  Colin L. Perry

IPC: H02H3/22 ,  H02H9/04 ,  H05K1/02 ,  H01L23/50

CPC classification number: H05K1/0231 ,  H01L23/50 ,  H01L2924/0002 ,  H02H9/04 ,  H05K1/025 ,  H05K2201/09672 ,  H01L2924/00

Abstract: In various embodiments, apparatuses and methods are disclosed that may be able to implement a multi-layer, three dimensional routing between a decoupling component and an input port for a SoC or MCM. A three dimensional (3D) structure may provide a defined current return path from the decoupling component to the input port. The current return path may be constrained by design to provide an equal and opposite electromagnetic flux to the input port thereby reducing series inductance between the input port and the decoupling component.

Abstract translation: 在各种实施例中，公开了可以在去耦组件和用于SoC或MCM的输入端口之间实现多层三维路由的装置和方法。 三维（3D）结构可以提供从去耦组件到输入端口的定义的当前返回路径。 电流返回路径可能被设计约束以向输入端口提供相等且相反的电磁通量，从而减小输入端口和去耦部件之间的串联电感。