公开(公告)号：US10763218B2

公开(公告)日：2020-09-01

申请号：US16079105

申请日：2016-03-24

Applicant: Intel Corporation

Inventor： Sruti Chigullapalli ,  Leslie Fitch ,  Boping Wu

IPC: H01L23/552 ,  H01L23/60 ,  H01L23/10 ,  H01L23/367 ,  H01L23/498 ,  H01L25/065 ,  H05K9/00 ,  H05K7/20 ,  H01L23/42

Abstract: An electrical device includes at least one electrical component arranged on a carrier substrate and sidewalls of an electromagnetic shielding encapsulation arranged on the carrier substrate. The sidewalls of the electromagnetic shielding encapsulation laterally surround the at least one electrical component. Further, the electrical device includes a heat sink mounted to the sidewalls of the electromagnetic shielding encapsulation. The heat sink forms a cap of the electromagnetic shielding encapsulation and the heat sink includes surface-enlarging structures at a front side of the heat sink.

公开(公告)号：US20180270948A1

公开(公告)日：2018-09-20

申请号：US15675883

申请日：2017-08-14

Applicant: Intel Corporation

Inventor： William L. Barber ,  Keith Pinson ,  Andrew P. Collins ,  Boping Wu ,  Isaac Ali ,  Colin L. Perry

IPC: H05K1/02 ,  H02H9/04 ,  H01L23/50

CPC classification number: H05K1/0231 ,  H01L23/50 ,  H01L2924/0002 ,  H02H9/04 ,  H05K1/025 ,  H05K2201/09672 ,  H01L2924/00

Abstract: In various embodiments, apparatuses and methods are disclosed that may be able to implement a multi-layer, three dimensional routing between a decoupling component and an input port for a SoC or MCM. A three dimensional (3D) structure may provide a defined current return path from the decoupling component to the input port. The current return path may be constrained by design to provide an equal and opposite electromagnetic flux to the input port thereby reducing series inductance between the input port and the decoupling component.

公开(公告)号：US10015878B2

公开(公告)日：2018-07-03

申请号：US14945762

申请日：2015-11-19

Applicant: Intel Corporation

Inventor： William L. Barber ,  Keith Pinson ,  Andrew P. Collins ,  Boping Wu ,  Isaac Ali ,  Colin L. Perry

IPC: H02H9/04 ,  H05K1/02 ,  H01L23/50

CPC classification number: H05K1/0231 ,  H01L23/50 ,  H01L2924/0002 ,  H02H9/04 ,  H05K1/025 ,  H05K2201/09672 ,  H01L2924/00

Abstract: In various embodiments, apparatuses and methods are disclosed that may be able to implement a multi-layer, three dimensional routing between a decoupling component and an input port for a SoC or MCM. A three dimensional (3D) structure may provide a defined current return path from the decoupling component to the input port. The current return path may be constrained by design to provide an equal and opposite electromagnetic flux to the input port thereby reducing series inductance between the input port and the decoupling component.

公开(公告)号：US09485854B2

公开(公告)日：2016-11-01

申请号：US14464279

申请日：2014-08-20

Applicant: Intel Corporation

Inventor： Shaowu Huang ,  Kai Xiao ,  Beom-Taek Lee ,  Boping Wu ,  Xiaoning Ye

IPC: H05K1/02 ,  H01P3/08 ,  H01P11/00 ,  H05K1/09 ,  H05K3/30 ,  H05K1/18 ,  G06F1/16 ,  H01P1/26 ,  H01P5/16 ,  H04L25/03

CPC classification number: H05K1/023 ,  G06F1/16 ,  H01P1/268 ,  H01P3/08 ,  H01P5/16 ,  H01P11/003 ,  H01R12/737 ,  H01R13/6461 ,  H04L25/03006 ,  H05K1/0216 ,  H05K1/0231 ,  H05K1/0243 ,  H05K1/0246 ,  H05K1/0268 ,  H05K1/09 ,  H05K1/181 ,  H05K3/22 ,  H05K3/303 ,  H05K3/4007 ,  H05K2201/10159 ,  H05K2201/10204

Abstract: Embodiments of the present disclosure are directed toward techniques and configurations for electrical signal absorption in an interconnect disposed in a printed circuit board (PCB) assembly. In one instance, a PCB assembly may comprise a substrate, and an interconnect formed in the substrate to route an electrical signal within the PCB. The interconnect may be coupled with a connecting component that is disposed on a surface of the PCB. An absorbing material may be disposed on the PCB to be in direct contact with at least a portion of the connecting component to at least partially absorb a portion of the electrical signal. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及布置在印刷电路板（PCB）组件中的互连件中的电信号吸收的技术和配置。 在一种情况下，PCB组件可以包括衬底和形成在衬底中以在PCB内布置电信号的互连。 互连可以与布置在PCB的表面上的连接部件耦合。 吸收材料可以设置在PCB上以与连接部件的至少一部分直接接触，以至少部分地吸收电信号的一部分。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20160057851A1

公开(公告)日：2016-02-25

申请号：US14464279

申请日：2014-08-20

Applicant: Intel Corporation

Inventor： Shaowu Huang ,  Kai Xiao ,  Beom-Taek Lee ,  Boping Wu ,  Xiaoning Ye

IPC: H05K1/02 ,  H01P3/08 ,  H01P11/00 ,  H05K1/09 ,  H05K3/30 ,  H05K1/18 ,  G06F1/16

CPC classification number: H05K1/023 ,  G06F1/16 ,  H01P1/268 ,  H01P3/08 ,  H01P5/16 ,  H01P11/003 ,  H01R12/737 ,  H01R13/6461 ,  H04L25/03006 ,  H05K1/0216 ,  H05K1/0231 ,  H05K1/0243 ,  H05K1/0246 ,  H05K1/0268 ,  H05K1/09 ,  H05K1/181 ,  H05K3/22 ,  H05K3/303 ,  H05K3/4007 ,  H05K2201/10159 ,  H05K2201/10204

Abstract: Embodiments of the present disclosure are directed toward techniques and configurations for electrical signal absorption in an interconnect disposed in a printed circuit board (PCB) assembly. In one instance, a PCB assembly may comprise a substrate, and an interconnect formed in the substrate to route an electrical signal within the PCB. The interconnect may be coupled with a connecting component that is disposed on a surface of the PCB. An absorbing material may be disposed on the PCB to be in direct contact with at least a portion of the connecting component to at least partially absorb a portion of the electrical signal. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及布置在印刷电路板（PCB）组件中的互连件中的电信号吸收的技术和配置。 在一种情况下，PCB组件可以包括衬底和形成在衬底中以在PCB内布置电信号的互连。 互连可以与布置在PCB的表面上的连接部件耦合。 吸收材料可以设置在PCB上以与连接部件的至少一部分直接接触，以至少部分地吸收电信号的一部分。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20190074252A1

公开(公告)日：2019-03-07

申请号：US16079105

申请日：2016-03-24

Applicant: Intel Corporation

Inventor： Sruti Chigullapalli ,  Leslie Fitch ,  Boping Wu

IPC: H01L23/552 ,  H01L23/10 ,  H01L23/367 ,  H01L23/60

CPC classification number: H01L23/552 ,  H01L23/10 ,  H01L23/367 ,  H01L23/42 ,  H01L23/49827 ,  H01L23/60 ,  H01L25/065 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2224/73253 ,  H05K7/20409 ,  H05K9/0015 ,  H05K9/0032

Abstract: An electrical device includes at least one electrical component arranged on a carrier substrate and sidewalls of an electromagnetic shielding encapsulation arranged on the carrier substrate. The sidewalls of the electromagnetic shielding encapsulation laterally surround the at least one electrical component. Further, the electrical device includes a heat sink mounted to the sidewalls of the electromagnetic shielding encapsulation. The heat sink forms a cap of the electromagnetic shielding encapsulation and the heat sink includes surface-enlarging structures at a front side of the heat sink.

公开(公告)号：US20170006698A1

公开(公告)日：2017-01-05

申请号：US15265704

申请日：2016-09-14

Applicant: Intel Corporation

Inventor： Shaowu Huang ,  Kai Xiao ,  Beom-Taek Lee ,  Boping Wu ,  Xiaoning Ye

IPC: H01P1/24 ,  H05K1/18 ,  H05K3/40 ,  H05K3/22 ,  H01P3/08 ,  H01P11/00 ,  H01R12/73 ,  H01R13/6461 ,  H05K1/02 ,  H01P1/26

CPC classification number: H05K1/023 ,  G06F1/16 ,  H01P1/268 ,  H01P3/08 ,  H01P5/16 ,  H01P11/003 ,  H01R12/737 ,  H01R13/6461 ,  H04L25/03006 ,  H05K1/0216 ,  H05K1/0231 ,  H05K1/0243 ,  H05K1/0246 ,  H05K1/0268 ,  H05K1/09 ,  H05K1/181 ,  H05K3/22 ,  H05K3/303 ,  H05K3/4007 ,  H05K2201/10159 ,  H05K2201/10204

Abstract: Embodiments of the present disclosure are directed toward techniques and configurations for electrical signal absorption in an interconnect disposed in a printed circuit board (PCB) assembly. In one instance, a PCB assembly may comprise a substrate, and an interconnect formed in the substrate to route an electrical signal within the PCB. The interconnect may be coupled with a connecting component that is disposed on a surface of the PCB. An absorbing material may be disposed on the PCB to be in direct contact with at least a portion of the connecting component to at least partially absorb a portion of the electrical signal. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及布置在印刷电路板（PCB）组件中的互连件中的电信号吸收的技术和配置。 在一种情况下，PCB组件可以包括衬底和形成在衬底中以在PCB内布置电信号的互连。 互连可以与布置在PCB的表面上的连接部件耦合。 吸收材料可以设置在PCB上以与连接部件的至少一部分直接接触，以至少部分地吸收电信号的一部分。 可以描述和/或要求保护其他实施例。

公开(公告)号：US09750129B2

公开(公告)日：2017-08-29

申请号：US15265704

申请日：2016-09-14

Applicant: Intel Corporation

Inventor： Shaowu Huang ,  Kai Xiao ,  Beom-Taek Lee ,  Boping Wu ,  Xiaoning Ye

IPC: H01P1/24 ,  H01P1/26 ,  H01P11/00 ,  H01P3/08 ,  H01R12/73 ,  H01R13/6461 ,  H05K1/02 ,  H05K1/18 ,  H05K3/22 ,  H05K3/40 ,  G06F1/16 ,  H05K1/09 ,  H01P5/16 ,  H04L25/03 ,  H05K3/30

CPC classification number: H05K1/023 ,  G06F1/16 ,  H01P1/268 ,  H01P3/08 ,  H01P5/16 ,  H01P11/003 ,  H01R12/737 ,  H01R13/6461 ,  H04L25/03006 ,  H05K1/0216 ,  H05K1/0231 ,  H05K1/0243 ,  H05K1/0246 ,  H05K1/0268 ,  H05K1/09 ,  H05K1/181 ,  H05K3/22 ,  H05K3/303 ,  H05K3/4007 ,  H05K2201/10159 ,  H05K2201/10204

Abstract: Embodiments of the present disclosure are directed toward techniques and configurations for electrical signal absorption in an interconnect disposed in a printed circuit board (PCB) assembly. In one instance, a PCB assembly may comprise a substrate, and an interconnect formed in the substrate to route an electrical signal within the PCB. The interconnect may be coupled with a connecting component that is disposed on a surface of the PCB. An absorbing material may be disposed on the PCB to be in direct contact with at least a portion of the connecting component to at least partially absorb a portion of the electrical signal. Other embodiments may be described and/or claimed.

公开(公告)号：US20160309580A1

公开(公告)日：2016-10-20

申请号：US14945762

申请日：2015-11-19

Applicant: Intel Corporation

Inventor： William L. Barber ,  Keith Pinson ,  Andrew P. Collins ,  Boping Wu ,  Isaac Ali ,  Colin L. Perry

IPC: H05K1/02 ,  H01L23/50

CPC classification number: H05K1/0231 ,  H01L23/50 ,  H01L2924/0002 ,  H02H9/04 ,  H05K1/025 ,  H05K2201/09672 ,  H01L2924/00

Abstract: In various embodiments, apparatuses and methods are disclosed that may be able to implement a multi-layer, three dimensional routing between a decoupling component and an input port for a SoC or MCM. A three dimensional (3D) structure may provide a defined current return path from the decoupling component to the input port. The current return path may be constrained by design to provide an equal and opposite electromagnetic flux to the input port thereby reducing series inductance between the input port and the decoupling component.

公开(公告)号：US09225164B2

公开(公告)日：2015-12-29

申请号：US14534979

申请日：2014-11-06

Applicant: Intel Corporation

Inventor： William L. Barber ,  Keith Pinson ,  Andrew P. Collins ,  Boping Wu ,  Isaac Ali ,  Colin L. Perry

IPC: H02H3/22 ,  H02H9/04 ,  H05K1/02 ,  H01L23/50

CPC classification number: H05K1/0231 ,  H01L23/50 ,  H01L2924/0002 ,  H02H9/04 ,  H05K1/025 ,  H05K2201/09672 ,  H01L2924/00

Abstract: In various embodiments, apparatuses and methods are disclosed that may be able to implement a multi-layer, three dimensional routing between a decoupling component and an input port for a SoC or MCM. A three dimensional (3D) structure may provide a defined current return path from the decoupling component to the input port. The current return path may be constrained by design to provide an equal and opposite electromagnetic flux to the input port thereby reducing series inductance between the input port and the decoupling component.

Abstract translation: 在各种实施例中，公开了可以在去耦组件和用于SoC或MCM的输入端口之间实现多层三维路由的装置和方法。 三维（3D）结构可以提供从去耦组件到输入端口的定义的当前返回路径。 电流返回路径可能被设计约束以向输入端口提供相等且相反的电磁通量，从而减小输入端口和去耦部件之间的串联电感。