公开(公告)号：US10452586B2

公开(公告)日：2019-10-22

申请号：US15488929

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Altug Koker ,  Joydeep Ray ,  Kiran C Veernapu ,  Balaji Vembu ,  Vasanth Ranganathan ,  Prasoonkumar Surti

IPC: G06F13/40 ,  G06F12/0846 ,  G06F9/54 ,  G06F13/42 ,  G06T1/60 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0831

Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to monitor a thread switching overhead parameter for an application executing in a processing system and in response to a determination that the thread switching overhead parameter exceeds a threshold, to activate a thread management algorithm to reduce thread switching in the processing system. Other embodiments are also disclosed and claimed.

公开(公告)号：US10410399B2

公开(公告)日：2019-09-10

申请号：US15350864

申请日：2016-11-14

Applicant: Intel Corporation

Inventor： Kiran C Veernapu

IPC: G06T15/00 ,  G06T15/04

Abstract: Methods and apparatus relating to techniques for. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to determine a first line and a second line which define a chord to approximate a curve in two-dimensional (2D) space; and extend first line and the second line to a three-dimensional (3D) space using a line approximation between the 2D space and the 3D space. Other embodiments are also disclosed and claimed.

公开(公告)号：US20180300130A1

公开(公告)日：2018-10-18

申请号：US15488929

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Altug Koker ,  Joydeep Ray ,  Kiran C Veernapu ,  Balaji Vembu ,  Vasanth Ranganathan ,  Prasoonkumar Surti

IPC: G06F9/30 ,  G06F12/0846 ,  G06F9/54 ,  G06F13/42 ,  G06F13/40 ,  G06T1/20

Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to monitor a thread switching overhead parameter for an application executing in a processing system and in response to a determination that the thread switching overhead parameter exceeds a threshold, to activate a thread management algorithm to reduce thread switching in the processing system. Other embodiments are also disclosed and claimed.