Abstract:
A processing device (30, 710) for reducing scan traffic is provided. The processing device (30, 710) comprises one or more interfaces (32, 718) configured to transmit information to at least one register access interface (759, 761) and processing circuitry (34) configured to control the one or more interfaces. Further, the processing circuitry (34) is configured to obtain register parameters of at least one functional unit (760, 762) of a processing unit (750) and to generate an improved bulk register comprising the register parameters of the at least one functional unit.
Abstract:
Examples described herein relate to a central processing unit (CPU) that includes at least two cores, at least two caching agents (CAs), and circuitry to monitor a workload mapped to a CA of the at least two CAs and adjust the workload allocated to the CA to allocation among the CA and at least one other CA of the at least two CAs based on the monitored workload.
Abstract:
Technologies for authenticating a user to a computing device include determining a hair follicle pattern of a portion of the user's skin and comparing the determined hair follicle pattern to an authenticated hair follicle pattern to authenticate the user. The hair follicle pattern of the portion of the user's skin may, be generated by a camera of the computing device, and the authenticated hair follicle pattern may be stored in a secure storage of the computing device. Features of the computing device may be enabled based on the particular authenticated hair follicle pattern to which the determined hair follicle matches. Additionally, in some embodiments, one or more additional biometric authentications may be used, and the user may be authenticated based on the particular combination of the authenticated hair follicle pattern and the additional biometric authentication(s).
Abstract:
A method is described. The method includes recognizing different latencies and/or bandwidths between different levels of a system memory and different memory access requestors of a computing system. The system memory includes the different levels and different technologies. The method also includes allocating each of the memory access requestors with a respective region of the system memory having an appropriate latency and/or bandwidth.